701 lines
15 KiB
C
701 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "idxd.h"
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#include "registers.h"
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static int idxd_cmd_wait(struct idxd_device *idxd, u32 *status, int timeout);
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static int idxd_cmd_send(struct idxd_device *idxd, int cmd_code, u32 operand);
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/* Interrupt control bits */
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int idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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union msix_perm perm;
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u32 offset;
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if (vec_id < 0 || vec_id >= msixcnt)
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return -EINVAL;
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offset = idxd->msix_perm_offset + vec_id * 8;
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perm.bits = ioread32(idxd->reg_base + offset);
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perm.ignore = 1;
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iowrite32(perm.bits, idxd->reg_base + offset);
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return 0;
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}
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void idxd_mask_msix_vectors(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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int i, rc;
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for (i = 0; i < msixcnt; i++) {
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rc = idxd_mask_msix_vector(idxd, i);
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if (rc < 0)
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dev_warn(&pdev->dev,
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"Failed disabling msix vec %d\n", i);
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}
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}
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int idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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union msix_perm perm;
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u32 offset;
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if (vec_id < 0 || vec_id >= msixcnt)
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return -EINVAL;
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offset = idxd->msix_perm_offset + vec_id * 8;
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perm.bits = ioread32(idxd->reg_base + offset);
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perm.ignore = 0;
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iowrite32(perm.bits, idxd->reg_base + offset);
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/*
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* A readback from the device ensures that any previously generated
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* completion record writes are visible to software based on PCI
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* ordering rules.
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*/
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perm.bits = ioread32(idxd->reg_base + offset);
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return 0;
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}
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void idxd_unmask_error_interrupts(struct idxd_device *idxd)
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{
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union genctrl_reg genctrl;
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genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
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genctrl.softerr_int_en = 1;
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iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
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}
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void idxd_mask_error_interrupts(struct idxd_device *idxd)
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{
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union genctrl_reg genctrl;
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genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
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genctrl.softerr_int_en = 0;
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iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
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}
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static void free_hw_descs(struct idxd_wq *wq)
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{
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int i;
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for (i = 0; i < wq->num_descs; i++)
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kfree(wq->hw_descs[i]);
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kfree(wq->hw_descs);
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}
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static int alloc_hw_descs(struct idxd_wq *wq, int num)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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int i;
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int node = dev_to_node(dev);
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wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
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GFP_KERNEL, node);
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if (!wq->hw_descs)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
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GFP_KERNEL, node);
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if (!wq->hw_descs[i]) {
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free_hw_descs(wq);
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return -ENOMEM;
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}
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}
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return 0;
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}
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static void free_descs(struct idxd_wq *wq)
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{
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int i;
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for (i = 0; i < wq->num_descs; i++)
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kfree(wq->descs[i]);
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kfree(wq->descs);
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}
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static int alloc_descs(struct idxd_wq *wq, int num)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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int i;
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int node = dev_to_node(dev);
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wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
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GFP_KERNEL, node);
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if (!wq->descs)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
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GFP_KERNEL, node);
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if (!wq->descs[i]) {
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free_descs(wq);
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return -ENOMEM;
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}
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}
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return 0;
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}
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/* WQ control bits */
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int idxd_wq_alloc_resources(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct idxd_group *group = wq->group;
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struct device *dev = &idxd->pdev->dev;
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int rc, num_descs, i;
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if (wq->type != IDXD_WQT_KERNEL)
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return 0;
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num_descs = wq->size +
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idxd->hw.gen_cap.max_descs_per_engine * group->num_engines;
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wq->num_descs = num_descs;
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rc = alloc_hw_descs(wq, num_descs);
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if (rc < 0)
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return rc;
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wq->compls_size = num_descs * sizeof(struct dsa_completion_record);
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wq->compls = dma_alloc_coherent(dev, wq->compls_size,
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&wq->compls_addr, GFP_KERNEL);
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if (!wq->compls) {
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rc = -ENOMEM;
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goto fail_alloc_compls;
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}
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rc = alloc_descs(wq, num_descs);
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if (rc < 0)
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goto fail_alloc_descs;
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rc = sbitmap_init_node(&wq->sbmap, num_descs, -1, GFP_KERNEL,
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dev_to_node(dev));
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if (rc < 0)
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goto fail_sbitmap_init;
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for (i = 0; i < num_descs; i++) {
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struct idxd_desc *desc = wq->descs[i];
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desc->hw = wq->hw_descs[i];
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desc->completion = &wq->compls[i];
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desc->compl_dma = wq->compls_addr +
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sizeof(struct dsa_completion_record) * i;
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desc->id = i;
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desc->wq = wq;
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dma_async_tx_descriptor_init(&desc->txd, &wq->dma_chan);
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desc->txd.tx_submit = idxd_dma_tx_submit;
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}
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return 0;
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fail_sbitmap_init:
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free_descs(wq);
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fail_alloc_descs:
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dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
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fail_alloc_compls:
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free_hw_descs(wq);
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return rc;
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}
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void idxd_wq_free_resources(struct idxd_wq *wq)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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if (wq->type != IDXD_WQT_KERNEL)
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return;
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free_hw_descs(wq);
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free_descs(wq);
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dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
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sbitmap_free(&wq->sbmap);
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}
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int idxd_wq_enable(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 status;
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int rc;
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lockdep_assert_held(&idxd->dev_lock);
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if (wq->state == IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d already enabled\n", wq->id);
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return -ENXIO;
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}
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rc = idxd_cmd_send(idxd, IDXD_CMD_ENABLE_WQ, wq->id);
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if (rc < 0)
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return rc;
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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if (status != IDXD_CMDSTS_SUCCESS &&
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status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
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dev_dbg(dev, "WQ enable failed: %#x\n", status);
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return -ENXIO;
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}
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wq->state = IDXD_WQ_ENABLED;
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dev_dbg(dev, "WQ %d enabled\n", wq->id);
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return 0;
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}
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int idxd_wq_disable(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 status, operand;
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int rc;
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lockdep_assert_held(&idxd->dev_lock);
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dev_dbg(dev, "Disabling WQ %d\n", wq->id);
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if (wq->state != IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
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return 0;
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}
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operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
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rc = idxd_cmd_send(idxd, IDXD_CMD_DISABLE_WQ, operand);
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if (rc < 0)
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return rc;
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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if (status != IDXD_CMDSTS_SUCCESS) {
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dev_dbg(dev, "WQ disable failed: %#x\n", status);
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return -ENXIO;
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}
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wq->state = IDXD_WQ_DISABLED;
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dev_dbg(dev, "WQ %d disabled\n", wq->id);
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return 0;
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}
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int idxd_wq_map_portal(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct pci_dev *pdev = idxd->pdev;
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struct device *dev = &pdev->dev;
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resource_size_t start;
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start = pci_resource_start(pdev, IDXD_WQ_BAR);
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start = start + wq->id * IDXD_PORTAL_SIZE;
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wq->dportal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
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if (!wq->dportal)
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return -ENOMEM;
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dev_dbg(dev, "wq %d portal mapped at %p\n", wq->id, wq->dportal);
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return 0;
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}
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void idxd_wq_unmap_portal(struct idxd_wq *wq)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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devm_iounmap(dev, wq->dportal);
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}
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/* Device control bits */
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static inline bool idxd_is_enabled(struct idxd_device *idxd)
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{
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union gensts_reg gensts;
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gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
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if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
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return true;
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return false;
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}
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static int idxd_cmd_wait(struct idxd_device *idxd, u32 *status, int timeout)
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{
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u32 sts, to = timeout;
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lockdep_assert_held(&idxd->dev_lock);
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sts = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
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while (sts & IDXD_CMDSTS_ACTIVE && --to) {
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cpu_relax();
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sts = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
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}
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if (to == 0 && sts & IDXD_CMDSTS_ACTIVE) {
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dev_warn(&idxd->pdev->dev, "%s timed out!\n", __func__);
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*status = 0;
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return -EBUSY;
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}
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*status = sts;
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return 0;
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}
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static int idxd_cmd_send(struct idxd_device *idxd, int cmd_code, u32 operand)
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{
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union idxd_command_reg cmd;
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int rc;
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u32 status;
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lockdep_assert_held(&idxd->dev_lock);
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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memset(&cmd, 0, sizeof(cmd));
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cmd.cmd = cmd_code;
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cmd.operand = operand;
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dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
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__func__, cmd_code, operand);
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iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
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return 0;
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}
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int idxd_device_enable(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int rc;
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u32 status;
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lockdep_assert_held(&idxd->dev_lock);
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if (idxd_is_enabled(idxd)) {
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dev_dbg(dev, "Device already enabled\n");
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return -ENXIO;
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}
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rc = idxd_cmd_send(idxd, IDXD_CMD_ENABLE_DEVICE, 0);
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if (rc < 0)
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return rc;
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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/* If the command is successful or if the device was enabled */
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if (status != IDXD_CMDSTS_SUCCESS &&
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status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
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dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
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return -ENXIO;
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}
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idxd->state = IDXD_DEV_ENABLED;
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return 0;
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}
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int idxd_device_disable(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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int rc;
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u32 status;
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lockdep_assert_held(&idxd->dev_lock);
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if (!idxd_is_enabled(idxd)) {
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dev_dbg(dev, "Device is not enabled\n");
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return 0;
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}
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rc = idxd_cmd_send(idxd, IDXD_CMD_DISABLE_DEVICE, 0);
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if (rc < 0)
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return rc;
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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/* If the command is successful or if the device was disabled */
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if (status != IDXD_CMDSTS_SUCCESS &&
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!(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
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dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
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rc = -ENXIO;
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return rc;
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}
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idxd->state = IDXD_DEV_CONF_READY;
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return 0;
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}
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int __idxd_device_reset(struct idxd_device *idxd)
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{
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u32 status;
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int rc;
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rc = idxd_cmd_send(idxd, IDXD_CMD_RESET_DEVICE, 0);
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if (rc < 0)
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return rc;
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rc = idxd_cmd_wait(idxd, &status, IDXD_REG_TIMEOUT);
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if (rc < 0)
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return rc;
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return 0;
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}
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int idxd_device_reset(struct idxd_device *idxd)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&idxd->dev_lock, flags);
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rc = __idxd_device_reset(idxd);
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spin_unlock_irqrestore(&idxd->dev_lock, flags);
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return rc;
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}
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/* Device configuration bits */
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static void idxd_group_config_write(struct idxd_group *group)
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{
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struct idxd_device *idxd = group->idxd;
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struct device *dev = &idxd->pdev->dev;
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int i;
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u32 grpcfg_offset;
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dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
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/* setup GRPWQCFG */
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for (i = 0; i < 4; i++) {
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grpcfg_offset = idxd->grpcfg_offset +
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group->id * 64 + i * sizeof(u64);
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iowrite64(group->grpcfg.wqs[i],
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idxd->reg_base + grpcfg_offset);
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dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
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group->id, i, grpcfg_offset,
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ioread64(idxd->reg_base + grpcfg_offset));
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}
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/* setup GRPENGCFG */
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grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 32;
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iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
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dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
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grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
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/* setup GRPFLAGS */
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grpcfg_offset = idxd->grpcfg_offset + group->id * 64 + 40;
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iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
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dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
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group->id, grpcfg_offset,
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ioread32(idxd->reg_base + grpcfg_offset));
|
|
}
|
|
|
|
static int idxd_groups_config_write(struct idxd_device *idxd)
|
|
|
|
{
|
|
union gencfg_reg reg;
|
|
int i;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
|
|
/* Setup bandwidth token limit */
|
|
if (idxd->token_limit) {
|
|
reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
|
|
reg.token_limit = idxd->token_limit;
|
|
iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
|
|
}
|
|
|
|
dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
|
|
ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
struct idxd_group *group = &idxd->groups[i];
|
|
|
|
idxd_group_config_write(group);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wq_config_write(struct idxd_wq *wq)
|
|
{
|
|
struct idxd_device *idxd = wq->idxd;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 wq_offset;
|
|
int i;
|
|
|
|
if (!wq->group)
|
|
return 0;
|
|
|
|
memset(&wq->wqcfg, 0, sizeof(union wqcfg));
|
|
|
|
/* byte 0-3 */
|
|
wq->wqcfg.wq_size = wq->size;
|
|
|
|
if (wq->size == 0) {
|
|
dev_warn(dev, "Incorrect work queue size: 0\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* bytes 4-7 */
|
|
wq->wqcfg.wq_thresh = wq->threshold;
|
|
|
|
/* byte 8-11 */
|
|
wq->wqcfg.priv = !!(wq->type == IDXD_WQT_KERNEL);
|
|
wq->wqcfg.mode = 1;
|
|
|
|
wq->wqcfg.priority = wq->priority;
|
|
|
|
/* bytes 12-15 */
|
|
wq->wqcfg.max_xfer_shift = idxd->hw.gen_cap.max_xfer_shift;
|
|
wq->wqcfg.max_batch_shift = idxd->hw.gen_cap.max_batch_shift;
|
|
|
|
dev_dbg(dev, "WQ %d CFGs\n", wq->id);
|
|
for (i = 0; i < 8; i++) {
|
|
wq_offset = idxd->wqcfg_offset + wq->id * 32 + i * sizeof(u32);
|
|
iowrite32(wq->wqcfg.bits[i], idxd->reg_base + wq_offset);
|
|
dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
|
|
wq->id, i, wq_offset,
|
|
ioread32(idxd->reg_base + wq_offset));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wqs_config_write(struct idxd_device *idxd)
|
|
{
|
|
int i, rc;
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
struct idxd_wq *wq = &idxd->wqs[i];
|
|
|
|
rc = idxd_wq_config_write(wq);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idxd_group_flags_setup(struct idxd_device *idxd)
|
|
{
|
|
int i;
|
|
|
|
/* TC-A 0 and TC-B 1 should be defaults */
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
struct idxd_group *group = &idxd->groups[i];
|
|
|
|
if (group->tc_a == -1)
|
|
group->tc_a = group->grpcfg.flags.tc_a = 0;
|
|
else
|
|
group->grpcfg.flags.tc_a = group->tc_a;
|
|
if (group->tc_b == -1)
|
|
group->tc_b = group->grpcfg.flags.tc_b = 1;
|
|
else
|
|
group->grpcfg.flags.tc_b = group->tc_b;
|
|
group->grpcfg.flags.use_token_limit = group->use_token_limit;
|
|
group->grpcfg.flags.tokens_reserved = group->tokens_reserved;
|
|
if (group->tokens_allowed)
|
|
group->grpcfg.flags.tokens_allowed =
|
|
group->tokens_allowed;
|
|
else
|
|
group->grpcfg.flags.tokens_allowed = idxd->max_tokens;
|
|
}
|
|
}
|
|
|
|
static int idxd_engines_setup(struct idxd_device *idxd)
|
|
{
|
|
int i, engines = 0;
|
|
struct idxd_engine *eng;
|
|
struct idxd_group *group;
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
group = &idxd->groups[i];
|
|
group->grpcfg.engines = 0;
|
|
}
|
|
|
|
for (i = 0; i < idxd->max_engines; i++) {
|
|
eng = &idxd->engines[i];
|
|
group = eng->group;
|
|
|
|
if (!group)
|
|
continue;
|
|
|
|
group->grpcfg.engines |= BIT(eng->id);
|
|
engines++;
|
|
}
|
|
|
|
if (!engines)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wqs_setup(struct idxd_device *idxd)
|
|
{
|
|
struct idxd_wq *wq;
|
|
struct idxd_group *group;
|
|
int i, j, configured = 0;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
group = &idxd->groups[i];
|
|
for (j = 0; j < 4; j++)
|
|
group->grpcfg.wqs[j] = 0;
|
|
}
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
wq = &idxd->wqs[i];
|
|
group = wq->group;
|
|
|
|
if (!wq->group)
|
|
continue;
|
|
if (!wq->size)
|
|
continue;
|
|
|
|
if (!wq_dedicated(wq)) {
|
|
dev_warn(dev, "No shared workqueue support.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
|
|
configured++;
|
|
}
|
|
|
|
if (configured == 0)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int idxd_device_config(struct idxd_device *idxd)
|
|
{
|
|
int rc;
|
|
|
|
lockdep_assert_held(&idxd->dev_lock);
|
|
rc = idxd_wqs_setup(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = idxd_engines_setup(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
idxd_group_flags_setup(idxd);
|
|
|
|
rc = idxd_wqs_config_write(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = idxd_groups_config_write(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|