1044 lines
29 KiB
C
1044 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
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//
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// Copyright (C) 2014 Freescale Semiconductor, Inc.
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//
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// Author: Nicolin Chen <nicoleotsuka@gmail.com>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/pm_runtime.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "fsl_asrc.h"
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#define IDEAL_RATIO_DECIMAL_DEPTH 26
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#define pair_err(fmt, ...) \
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dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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#define pair_dbg(fmt, ...) \
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dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
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/* Sample rates are aligned with that defined in pcm.h file */
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static const u8 process_option[][12][2] = {
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/* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
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{{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
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{{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
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{{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
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{{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
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{{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
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{{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
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{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
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{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
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{{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
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{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
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{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
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{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
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{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
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};
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/* Corresponding to process_option */
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static int supported_input_rate[] = {
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5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
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96000, 176400, 192000,
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};
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static int supported_asrc_rate[] = {
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8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
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};
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/**
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* The following tables map the relationship between asrc_inclk/asrc_outclk in
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* fsl_asrc.h and the registers of ASRCSR
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*/
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static unsigned char input_clk_map_imx35[] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
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};
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static unsigned char output_clk_map_imx35[] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
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};
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/* i.MX53 uses the same map for input and output */
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static unsigned char input_clk_map_imx53[] = {
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/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
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0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
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};
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static unsigned char output_clk_map_imx53[] = {
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/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
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0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
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};
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static unsigned char *clk_map[2];
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/**
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* Request ASRC pair
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*
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* It assigns pair by the order of A->C->B because allocation of pair B,
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* within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
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* while pair A and pair C are comparatively independent.
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*/
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static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
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{
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enum asrc_pair_index index = ASRC_INVALID_PAIR;
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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struct device *dev = &asrc_priv->pdev->dev;
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unsigned long lock_flags;
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int i, ret = 0;
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spin_lock_irqsave(&asrc_priv->lock, lock_flags);
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for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
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if (asrc_priv->pair[i] != NULL)
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continue;
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index = i;
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if (i != ASRC_PAIR_B)
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break;
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}
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if (index == ASRC_INVALID_PAIR) {
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dev_err(dev, "all pairs are busy now\n");
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ret = -EBUSY;
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} else if (asrc_priv->channel_avail < channels) {
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dev_err(dev, "can't afford required channels: %d\n", channels);
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ret = -EINVAL;
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} else {
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asrc_priv->channel_avail -= channels;
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asrc_priv->pair[index] = pair;
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pair->channels = channels;
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pair->index = index;
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}
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spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
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return ret;
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}
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/**
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* Release ASRC pair
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*
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* It clears the resource from asrc_priv and releases the occupied channels.
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*/
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static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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enum asrc_pair_index index = pair->index;
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unsigned long lock_flags;
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/* Make sure the pair is disabled */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_ASRCEi_MASK(index), 0);
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spin_lock_irqsave(&asrc_priv->lock, lock_flags);
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asrc_priv->channel_avail += pair->channels;
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asrc_priv->pair[index] = NULL;
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pair->error = 0;
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spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
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}
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/**
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* Configure input and output thresholds
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*/
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static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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enum asrc_pair_index index = pair->index;
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
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ASRMCRi_EXTTHRSHi_MASK |
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ASRMCRi_INFIFO_THRESHOLD_MASK |
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ASRMCRi_OUTFIFO_THRESHOLD_MASK,
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ASRMCRi_EXTTHRSHi |
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ASRMCRi_INFIFO_THRESHOLD(in) |
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ASRMCRi_OUTFIFO_THRESHOLD(out));
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}
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/**
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* Calculate the total divisor between asrck clock rate and sample rate
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*
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* It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
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*/
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static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
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{
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u32 ps;
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/* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
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for (ps = 0; div > 8; ps++)
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div >>= 1;
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return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
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}
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/**
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* Calculate and set the ratio for Ideal Ratio mode only
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*
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* The ratio is a 32-bit fixed point value with 26 fractional bits.
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*/
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static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
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int inrate, int outrate)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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enum asrc_pair_index index = pair->index;
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unsigned long ratio;
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int i;
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if (!outrate) {
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pair_err("output rate should not be zero\n");
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return -EINVAL;
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}
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/* Calculate the intergal part of the ratio */
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ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
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/* ... and then the 26 depth decimal part */
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inrate %= outrate;
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for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
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inrate <<= 1;
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if (inrate < outrate)
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continue;
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ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
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inrate -= outrate;
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if (!inrate)
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break;
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}
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regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
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regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
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return 0;
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}
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/**
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* Configure the assigned ASRC pair
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*
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* It configures those ASRC registers according to a configuration instance
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* of struct asrc_config which includes in/output sample rate, width, channel
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* and clock settings.
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*/
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static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
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{
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struct asrc_config *config = pair->config;
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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enum asrc_pair_index index = pair->index;
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u32 inrate, outrate, indiv, outdiv;
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u32 clk_index[2], div[2];
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int in, out, channels;
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struct clk *clk;
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bool ideal;
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if (!config) {
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pair_err("invalid pair config\n");
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return -EINVAL;
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}
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/* Validate channels */
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if (config->channel_num < 1 || config->channel_num > 10) {
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pair_err("does not support %d channels\n", config->channel_num);
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return -EINVAL;
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}
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/* Validate output width */
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if (config->output_word_width == ASRC_WIDTH_8_BIT) {
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pair_err("does not support 8bit width output\n");
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return -EINVAL;
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}
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inrate = config->input_sample_rate;
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outrate = config->output_sample_rate;
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ideal = config->inclk == INCLK_NONE;
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/* Validate input and output sample rates */
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for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
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if (inrate == supported_input_rate[in])
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break;
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if (in == ARRAY_SIZE(supported_input_rate)) {
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pair_err("unsupported input sample rate: %dHz\n", inrate);
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return -EINVAL;
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}
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for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
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if (outrate == supported_asrc_rate[out])
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break;
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if (out == ARRAY_SIZE(supported_asrc_rate)) {
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pair_err("unsupported output sample rate: %dHz\n", outrate);
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return -EINVAL;
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}
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if ((outrate > 8000 && outrate < 30000) &&
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(outrate/inrate > 24 || inrate/outrate > 8)) {
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pair_err("exceed supported ratio range [1/24, 8] for \
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inrate/outrate: %d/%d\n", inrate, outrate);
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return -EINVAL;
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}
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/* Validate input and output clock sources */
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clk_index[IN] = clk_map[IN][config->inclk];
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clk_index[OUT] = clk_map[OUT][config->outclk];
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/* We only have output clock for ideal ratio mode */
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clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
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div[IN] = clk_get_rate(clk) / inrate;
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if (div[IN] == 0) {
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pair_err("failed to support input sample rate %dHz by asrck_%x\n",
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inrate, clk_index[ideal ? OUT : IN]);
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return -EINVAL;
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}
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clk = asrc_priv->asrck_clk[clk_index[OUT]];
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/* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
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if (ideal)
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div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
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else
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div[OUT] = clk_get_rate(clk) / outrate;
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if (div[OUT] == 0) {
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pair_err("failed to support output sample rate %dHz by asrck_%x\n",
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outrate, clk_index[OUT]);
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return -EINVAL;
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}
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/* Set the channel number */
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channels = config->channel_num;
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if (asrc_priv->channel_bits < 4)
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channels /= 2;
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/* Update channels for current pair */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
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ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
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ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
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/* Default setting: Automatic selection for processing mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_USRi_MASK(index), 0);
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/* Set the input and output clock sources */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
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ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
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ASRCSR_AICS(index, clk_index[IN]) |
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ASRCSR_AOCS(index, clk_index[OUT]));
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/* Calculate the input clock divisors */
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indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
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outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
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/* Suppose indiv and outdiv includes prescaler, so add its MASK too */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
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ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
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ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
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ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
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/* Implement word_width configurations */
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
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ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
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ASRMCR1i_OW16(config->output_word_width) |
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ASRMCR1i_IWD(config->input_word_width));
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/* Enable BUFFER STALL */
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regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
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ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
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/* Set default thresholds for input and output FIFO */
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fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
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ASRC_INPUTFIFO_THRESHOLD);
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/* Configure the following only for Ideal Ratio mode */
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if (!ideal)
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return 0;
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/* Clear ASTSx bit to use Ideal Ratio mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_ATSi_MASK(index), 0);
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/* Enable Ideal Ratio mode */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
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ASRCTR_IDR(index) | ASRCTR_USR(index));
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/* Apply configurations for pre- and post-processing */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
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ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
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ASRCFG_PREMOD(index, process_option[in][out][0]) |
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ASRCFG_POSTMOD(index, process_option[in][out][1]));
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return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
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}
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/**
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* Start the assigned ASRC pair
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*
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* It enables the assigned pair and makes it stopped at the stall level.
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*/
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static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
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{
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struct fsl_asrc *asrc_priv = pair->asrc_priv;
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enum asrc_pair_index index = pair->index;
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int reg, retry = 10, i;
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/* Enable the current pair */
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regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
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ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
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/* Wait for status of initialization */
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do {
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udelay(5);
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regmap_read(asrc_priv->regmap, REG_ASRCFG, ®);
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reg &= ASRCFG_INIRQi_MASK(index);
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} while (!reg && --retry);
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/* Make the input fifo to ASRC STALL level */
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regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®);
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for (i = 0; i < pair->channels * 4; i++)
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regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
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/* Enable overload interrupt */
|
|
regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
|
|
}
|
|
|
|
/**
|
|
* Stop the assigned ASRC pair
|
|
*/
|
|
static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
|
|
{
|
|
struct fsl_asrc *asrc_priv = pair->asrc_priv;
|
|
enum asrc_pair_index index = pair->index;
|
|
|
|
/* Stop the current pair */
|
|
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
|
|
ASRCTR_ASRCEi_MASK(index), 0);
|
|
}
|
|
|
|
/**
|
|
* Get DMA channel according to the pair and direction.
|
|
*/
|
|
struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
|
|
{
|
|
struct fsl_asrc *asrc_priv = pair->asrc_priv;
|
|
enum asrc_pair_index index = pair->index;
|
|
char name[4];
|
|
|
|
sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
|
|
|
|
return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
|
|
|
|
static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
|
|
int width = params_width(params);
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_asrc_pair *pair = runtime->private_data;
|
|
unsigned int channels = params_channels(params);
|
|
unsigned int rate = params_rate(params);
|
|
struct asrc_config config;
|
|
int word_width, ret;
|
|
|
|
ret = fsl_asrc_request_pair(channels, pair);
|
|
if (ret) {
|
|
dev_err(dai->dev, "fail to request asrc pair\n");
|
|
return ret;
|
|
}
|
|
|
|
pair->config = &config;
|
|
|
|
if (width == 16)
|
|
width = ASRC_WIDTH_16_BIT;
|
|
else
|
|
width = ASRC_WIDTH_24_BIT;
|
|
|
|
if (asrc_priv->asrc_width == 16)
|
|
word_width = ASRC_WIDTH_16_BIT;
|
|
else
|
|
word_width = ASRC_WIDTH_24_BIT;
|
|
|
|
config.pair = pair->index;
|
|
config.channel_num = channels;
|
|
config.inclk = INCLK_NONE;
|
|
config.outclk = OUTCLK_ASRCK1_CLK;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
config.input_word_width = width;
|
|
config.output_word_width = word_width;
|
|
config.input_sample_rate = rate;
|
|
config.output_sample_rate = asrc_priv->asrc_rate;
|
|
} else {
|
|
config.input_word_width = word_width;
|
|
config.output_word_width = width;
|
|
config.input_sample_rate = asrc_priv->asrc_rate;
|
|
config.output_sample_rate = rate;
|
|
}
|
|
|
|
ret = fsl_asrc_config_pair(pair);
|
|
if (ret) {
|
|
dev_err(dai->dev, "fail to config asrc pair\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_asrc_pair *pair = runtime->private_data;
|
|
|
|
if (pair)
|
|
fsl_asrc_release_pair(pair);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_asrc_pair *pair = runtime->private_data;
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
fsl_asrc_start_pair(pair);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
fsl_asrc_stop_pair(pair);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
|
|
.hw_params = fsl_asrc_dai_hw_params,
|
|
.hw_free = fsl_asrc_dai_hw_free,
|
|
.trigger = fsl_asrc_dai_trigger,
|
|
};
|
|
|
|
static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
|
|
{
|
|
struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
|
|
|
|
snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
|
|
&asrc_priv->dma_params_rx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
|
|
#define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
|
|
SNDRV_PCM_FMTBIT_S16_LE | \
|
|
SNDRV_PCM_FMTBIT_S20_3LE)
|
|
|
|
static struct snd_soc_dai_driver fsl_asrc_dai = {
|
|
.probe = fsl_asrc_dai_probe,
|
|
.playback = {
|
|
.stream_name = "ASRC-Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 10,
|
|
.rates = FSL_ASRC_RATES,
|
|
.formats = FSL_ASRC_FORMATS,
|
|
},
|
|
.capture = {
|
|
.stream_name = "ASRC-Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 10,
|
|
.rates = FSL_ASRC_RATES,
|
|
.formats = FSL_ASRC_FORMATS,
|
|
},
|
|
.ops = &fsl_asrc_dai_ops,
|
|
};
|
|
|
|
static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case REG_ASRCTR:
|
|
case REG_ASRIER:
|
|
case REG_ASRCNCR:
|
|
case REG_ASRCFG:
|
|
case REG_ASRCSR:
|
|
case REG_ASRCDR1:
|
|
case REG_ASRCDR2:
|
|
case REG_ASRSTR:
|
|
case REG_ASRPM1:
|
|
case REG_ASRPM2:
|
|
case REG_ASRPM3:
|
|
case REG_ASRPM4:
|
|
case REG_ASRPM5:
|
|
case REG_ASRTFR1:
|
|
case REG_ASRCCR:
|
|
case REG_ASRDOA:
|
|
case REG_ASRDOB:
|
|
case REG_ASRDOC:
|
|
case REG_ASRIDRHA:
|
|
case REG_ASRIDRLA:
|
|
case REG_ASRIDRHB:
|
|
case REG_ASRIDRLB:
|
|
case REG_ASRIDRHC:
|
|
case REG_ASRIDRLC:
|
|
case REG_ASR76K:
|
|
case REG_ASR56K:
|
|
case REG_ASRMCRA:
|
|
case REG_ASRFSTA:
|
|
case REG_ASRMCRB:
|
|
case REG_ASRFSTB:
|
|
case REG_ASRMCRC:
|
|
case REG_ASRFSTC:
|
|
case REG_ASRMCR1A:
|
|
case REG_ASRMCR1B:
|
|
case REG_ASRMCR1C:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case REG_ASRSTR:
|
|
case REG_ASRDIA:
|
|
case REG_ASRDIB:
|
|
case REG_ASRDIC:
|
|
case REG_ASRDOA:
|
|
case REG_ASRDOB:
|
|
case REG_ASRDOC:
|
|
case REG_ASRFSTA:
|
|
case REG_ASRFSTB:
|
|
case REG_ASRFSTC:
|
|
case REG_ASRCFG:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case REG_ASRCTR:
|
|
case REG_ASRIER:
|
|
case REG_ASRCNCR:
|
|
case REG_ASRCFG:
|
|
case REG_ASRCSR:
|
|
case REG_ASRCDR1:
|
|
case REG_ASRCDR2:
|
|
case REG_ASRSTR:
|
|
case REG_ASRPM1:
|
|
case REG_ASRPM2:
|
|
case REG_ASRPM3:
|
|
case REG_ASRPM4:
|
|
case REG_ASRPM5:
|
|
case REG_ASRTFR1:
|
|
case REG_ASRCCR:
|
|
case REG_ASRDIA:
|
|
case REG_ASRDIB:
|
|
case REG_ASRDIC:
|
|
case REG_ASRIDRHA:
|
|
case REG_ASRIDRLA:
|
|
case REG_ASRIDRHB:
|
|
case REG_ASRIDRLB:
|
|
case REG_ASRIDRHC:
|
|
case REG_ASRIDRLC:
|
|
case REG_ASR76K:
|
|
case REG_ASR56K:
|
|
case REG_ASRMCRA:
|
|
case REG_ASRMCRB:
|
|
case REG_ASRMCRC:
|
|
case REG_ASRMCR1A:
|
|
case REG_ASRMCR1B:
|
|
case REG_ASRMCR1C:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static struct reg_default fsl_asrc_reg[] = {
|
|
{ REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
|
|
{ REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
|
|
{ REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
|
|
{ REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
|
|
{ REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
|
|
{ REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
|
|
{ REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
|
|
{ REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
|
|
{ REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
|
|
{ REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
|
|
{ REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
|
|
{ REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
|
|
{ REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
|
|
{ REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
|
|
{ REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
|
|
{ REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
|
|
{ REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
|
|
{ REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
|
|
{ REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
|
|
{ REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
|
|
{ REG_ASRMCR1C, 0x0000 },
|
|
};
|
|
|
|
static const struct regmap_config fsl_asrc_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
|
|
.max_register = REG_ASRMCR1C,
|
|
.reg_defaults = fsl_asrc_reg,
|
|
.num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
|
|
.readable_reg = fsl_asrc_readable_reg,
|
|
.volatile_reg = fsl_asrc_volatile_reg,
|
|
.writeable_reg = fsl_asrc_writeable_reg,
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
/**
|
|
* Initialize ASRC registers with a default configurations
|
|
*/
|
|
static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
|
|
{
|
|
/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
|
|
regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
|
|
|
|
/* Disable interrupt by default */
|
|
regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
|
|
|
|
/* Apply recommended settings for parameters from Reference Manual */
|
|
regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
|
|
regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
|
|
regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
|
|
regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
|
|
regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
|
|
|
|
/* Base address for task queue FIFO. Set to 0x7C */
|
|
regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
|
|
ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
|
|
|
|
/* Set the processing clock for 76KHz to 133M */
|
|
regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
|
|
|
|
/* Set the processing clock for 56KHz to 133M */
|
|
return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
|
|
}
|
|
|
|
/**
|
|
* Interrupt handler for ASRC
|
|
*/
|
|
static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
|
|
{
|
|
struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
|
|
struct device *dev = &asrc_priv->pdev->dev;
|
|
enum asrc_pair_index index;
|
|
u32 status;
|
|
|
|
regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
|
|
|
|
/* Clean overload error */
|
|
regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
|
|
|
|
/*
|
|
* We here use dev_dbg() for all exceptions because ASRC itself does
|
|
* not care if FIFO overflowed or underrun while a warning in the
|
|
* interrupt would result a ridged conversion.
|
|
*/
|
|
for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
|
|
if (!asrc_priv->pair[index])
|
|
continue;
|
|
|
|
if (status & ASRSTR_ATQOL) {
|
|
asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
|
|
dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
|
|
}
|
|
|
|
if (status & ASRSTR_AOOL(index)) {
|
|
asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
|
|
pair_dbg("Output Task Overload\n");
|
|
}
|
|
|
|
if (status & ASRSTR_AIOL(index)) {
|
|
asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
|
|
pair_dbg("Input Task Overload\n");
|
|
}
|
|
|
|
if (status & ASRSTR_AODO(index)) {
|
|
asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
|
|
pair_dbg("Output Data Buffer has overflowed\n");
|
|
}
|
|
|
|
if (status & ASRSTR_AIDU(index)) {
|
|
asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
|
|
pair_dbg("Input Data Buffer has underflowed\n");
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int fsl_asrc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct fsl_asrc *asrc_priv;
|
|
struct resource *res;
|
|
void __iomem *regs;
|
|
int irq, ret, i;
|
|
char tmp[16];
|
|
|
|
asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
|
|
if (!asrc_priv)
|
|
return -ENOMEM;
|
|
|
|
asrc_priv->pdev = pdev;
|
|
|
|
/* Get the addresses and IRQ */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
asrc_priv->paddr = res->start;
|
|
|
|
asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
|
|
&fsl_asrc_regmap_config);
|
|
if (IS_ERR(asrc_priv->regmap)) {
|
|
dev_err(&pdev->dev, "failed to init regmap\n");
|
|
return PTR_ERR(asrc_priv->regmap);
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
|
|
dev_name(&pdev->dev), asrc_priv);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
|
|
if (IS_ERR(asrc_priv->mem_clk)) {
|
|
dev_err(&pdev->dev, "failed to get mem clock\n");
|
|
return PTR_ERR(asrc_priv->mem_clk);
|
|
}
|
|
|
|
asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
|
if (IS_ERR(asrc_priv->ipg_clk)) {
|
|
dev_err(&pdev->dev, "failed to get ipg clock\n");
|
|
return PTR_ERR(asrc_priv->ipg_clk);
|
|
}
|
|
|
|
asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
|
|
if (IS_ERR(asrc_priv->spba_clk))
|
|
dev_warn(&pdev->dev, "failed to get spba clock\n");
|
|
|
|
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
|
|
sprintf(tmp, "asrck_%x", i);
|
|
asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
|
|
if (IS_ERR(asrc_priv->asrck_clk[i])) {
|
|
dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
|
|
return PTR_ERR(asrc_priv->asrck_clk[i]);
|
|
}
|
|
}
|
|
|
|
if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
|
|
asrc_priv->channel_bits = 3;
|
|
clk_map[IN] = input_clk_map_imx35;
|
|
clk_map[OUT] = output_clk_map_imx35;
|
|
} else {
|
|
asrc_priv->channel_bits = 4;
|
|
clk_map[IN] = input_clk_map_imx53;
|
|
clk_map[OUT] = output_clk_map_imx53;
|
|
}
|
|
|
|
ret = fsl_asrc_init(asrc_priv);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
asrc_priv->channel_avail = 10;
|
|
|
|
ret = of_property_read_u32(np, "fsl,asrc-rate",
|
|
&asrc_priv->asrc_rate);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to get output rate\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "fsl,asrc-width",
|
|
&asrc_priv->asrc_width);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to get output width\n");
|
|
return ret;
|
|
}
|
|
|
|
if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
|
|
dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
|
|
asrc_priv->asrc_width = 24;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, asrc_priv);
|
|
pm_runtime_enable(&pdev->dev);
|
|
spin_lock_init(&asrc_priv->lock);
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
|
|
&fsl_asrc_dai, 1);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register ASoC DAI\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int fsl_asrc_runtime_resume(struct device *dev)
|
|
{
|
|
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
|
int i, ret;
|
|
|
|
ret = clk_prepare_enable(asrc_priv->mem_clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_prepare_enable(asrc_priv->ipg_clk);
|
|
if (ret)
|
|
goto disable_mem_clk;
|
|
if (!IS_ERR(asrc_priv->spba_clk)) {
|
|
ret = clk_prepare_enable(asrc_priv->spba_clk);
|
|
if (ret)
|
|
goto disable_ipg_clk;
|
|
}
|
|
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
|
|
ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
|
|
if (ret)
|
|
goto disable_asrck_clk;
|
|
}
|
|
|
|
return 0;
|
|
|
|
disable_asrck_clk:
|
|
for (i--; i >= 0; i--)
|
|
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
|
|
if (!IS_ERR(asrc_priv->spba_clk))
|
|
clk_disable_unprepare(asrc_priv->spba_clk);
|
|
disable_ipg_clk:
|
|
clk_disable_unprepare(asrc_priv->ipg_clk);
|
|
disable_mem_clk:
|
|
clk_disable_unprepare(asrc_priv->mem_clk);
|
|
return ret;
|
|
}
|
|
|
|
static int fsl_asrc_runtime_suspend(struct device *dev)
|
|
{
|
|
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
|
|
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
|
|
if (!IS_ERR(asrc_priv->spba_clk))
|
|
clk_disable_unprepare(asrc_priv->spba_clk);
|
|
clk_disable_unprepare(asrc_priv->ipg_clk);
|
|
clk_disable_unprepare(asrc_priv->mem_clk);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int fsl_asrc_suspend(struct device *dev)
|
|
{
|
|
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
|
|
|
regmap_read(asrc_priv->regmap, REG_ASRCFG,
|
|
&asrc_priv->regcache_cfg);
|
|
|
|
regcache_cache_only(asrc_priv->regmap, true);
|
|
regcache_mark_dirty(asrc_priv->regmap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_asrc_resume(struct device *dev)
|
|
{
|
|
struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
|
|
u32 asrctr;
|
|
|
|
/* Stop all pairs provisionally */
|
|
regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
|
|
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
|
|
ASRCTR_ASRCEi_ALL_MASK, 0);
|
|
|
|
/* Restore all registers */
|
|
regcache_cache_only(asrc_priv->regmap, false);
|
|
regcache_sync(asrc_priv->regmap);
|
|
|
|
regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
|
|
ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
|
|
ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
|
|
|
|
/* Restart enabled pairs */
|
|
regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
|
|
ASRCTR_ASRCEi_ALL_MASK, asrctr);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct dev_pm_ops fsl_asrc_pm = {
|
|
SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
|
|
};
|
|
|
|
static const struct of_device_id fsl_asrc_ids[] = {
|
|
{ .compatible = "fsl,imx35-asrc", },
|
|
{ .compatible = "fsl,imx53-asrc", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
|
|
|
|
static struct platform_driver fsl_asrc_driver = {
|
|
.probe = fsl_asrc_probe,
|
|
.driver = {
|
|
.name = "fsl-asrc",
|
|
.of_match_table = fsl_asrc_ids,
|
|
.pm = &fsl_asrc_pm,
|
|
},
|
|
};
|
|
module_platform_driver(fsl_asrc_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
|
|
MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
|
|
MODULE_ALIAS("platform:fsl-asrc");
|
|
MODULE_LICENSE("GPL v2");
|