375 lines
8.9 KiB
C
375 lines
8.9 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/pci.h>
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#include "amdgpu.h"
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#include "cgs_linux.h"
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struct amdgpu_cgs_device {
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struct cgs_device base;
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struct amdgpu_device *adev;
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};
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#define CGS_FUNC_ADEV \
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struct amdgpu_device *adev = \
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((struct amdgpu_cgs_device *)cgs_device)->adev
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static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t *mc_start, uint64_t *mc_size,
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uint64_t *mem_size)
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{
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return 0;
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}
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static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
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uint64_t size,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *kmem_handle, uint64_t *mcaddr)
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{
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return 0;
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}
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static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
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{
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return 0;
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}
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static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
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enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *handle)
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{
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return 0;
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}
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static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
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cgs_handle_t *handle)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
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void **map)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
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{
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/* TODO */
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return 0;
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}
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static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
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{
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CGS_FUNC_ADEV;
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return RREG32(offset);
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}
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static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
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uint32_t value)
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{
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CGS_FUNC_ADEV;
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WREG32(offset, value);
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}
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static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
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enum cgs_ind_reg space,
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unsigned index)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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case CGS_IND_REG__MMIO:
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return RREG32_IDX(index);
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case CGS_IND_REG__PCIE:
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return RREG32_PCIE(index);
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case CGS_IND_REG__SMC:
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return RREG32_SMC(index);
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case CGS_IND_REG__UVD_CTX:
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return RREG32_UVD_CTX(index);
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case CGS_IND_REG__DIDT:
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return RREG32_DIDT(index);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return 0;
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}
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WARN(1, "Invalid indirect register space");
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return 0;
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}
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static void amdgpu_cgs_write_ind_register(void *cgs_device,
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enum cgs_ind_reg space,
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unsigned index, uint32_t value)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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case CGS_IND_REG__MMIO:
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return WREG32_IDX(index, value);
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case CGS_IND_REG__PCIE:
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return WREG32_PCIE(index, value);
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case CGS_IND_REG__SMC:
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return WREG32_SMC(index, value);
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case CGS_IND_REG__UVD_CTX:
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return WREG32_UVD_CTX(index, value);
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case CGS_IND_REG__DIDT:
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return WREG32_DIDT(index, value);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return;
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}
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WARN(1, "Invalid indirect register space");
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}
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static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint8_t val;
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int ret = pci_read_config_byte(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_byte error"))
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return 0;
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return val;
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}
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static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint16_t val;
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int ret = pci_read_config_word(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_word error"))
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return 0;
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return val;
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}
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static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
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unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint32_t val;
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int ret = pci_read_config_dword(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_dword error"))
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return 0;
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return val;
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}
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static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
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uint8_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_byte(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_byte error");
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}
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static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
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uint16_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_word(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_word error");
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}
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static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
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uint32_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_dword(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_dword error");
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}
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static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
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unsigned table, uint16_t *size,
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uint8_t *frev, uint8_t *crev)
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{
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/* TODO */
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return NULL;
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}
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static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
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uint8_t *frev, uint8_t *crev)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
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void *args)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
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int active)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
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enum cgs_clock clock, unsigned freq)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
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enum cgs_engine engine, int powered)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
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enum cgs_clock clock,
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struct cgs_clock_limits *limits)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
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const uint32_t *voltages)
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{
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DRM_ERROR("not implemented");
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return -EPERM;
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}
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static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
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unsigned num_types,
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cgs_irq_source_set_func_t set,
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cgs_irq_handler_func_t handler,
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void *private_data)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
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{
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/* TODO */
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return 0;
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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amdgpu_cgs_gpu_mem_info,
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amdgpu_cgs_gmap_kmem,
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amdgpu_cgs_gunmap_kmem,
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amdgpu_cgs_alloc_gpu_mem,
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amdgpu_cgs_free_gpu_mem,
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amdgpu_cgs_gmap_gpu_mem,
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amdgpu_cgs_gunmap_gpu_mem,
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amdgpu_cgs_kmap_gpu_mem,
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amdgpu_cgs_kunmap_gpu_mem,
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amdgpu_cgs_read_register,
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amdgpu_cgs_write_register,
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amdgpu_cgs_read_ind_register,
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amdgpu_cgs_write_ind_register,
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amdgpu_cgs_read_pci_config_byte,
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amdgpu_cgs_read_pci_config_word,
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amdgpu_cgs_read_pci_config_dword,
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amdgpu_cgs_write_pci_config_byte,
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amdgpu_cgs_write_pci_config_word,
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amdgpu_cgs_write_pci_config_dword,
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amdgpu_cgs_atom_get_data_table,
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amdgpu_cgs_atom_get_cmd_table_revs,
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amdgpu_cgs_atom_exec_cmd_table,
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amdgpu_cgs_create_pm_request,
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amdgpu_cgs_destroy_pm_request,
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amdgpu_cgs_set_pm_request,
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amdgpu_cgs_pm_request_clock,
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amdgpu_cgs_pm_request_engine,
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amdgpu_cgs_pm_query_clock_limits,
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amdgpu_cgs_set_camera_voltages
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};
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static const struct cgs_os_ops amdgpu_cgs_os_ops = {
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amdgpu_cgs_import_gpu_mem,
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amdgpu_cgs_add_irq_source,
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amdgpu_cgs_irq_get,
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amdgpu_cgs_irq_put
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};
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void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
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{
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struct amdgpu_cgs_device *cgs_device =
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kmalloc(sizeof(*cgs_device), GFP_KERNEL);
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if (!cgs_device) {
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DRM_ERROR("Couldn't allocate CGS device structure\n");
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return NULL;
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}
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cgs_device->base.ops = &amdgpu_cgs_ops;
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cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
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cgs_device->adev = adev;
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return cgs_device;
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}
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void amdgpu_cgs_destroy_device(void *cgs_device)
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{
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kfree(cgs_device);
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}
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