194 lines
5.8 KiB
C
194 lines
5.8 KiB
C
#include <linux/serial.h>
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#include <asm/dma.h>
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#define NR_PORTS 4
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_GCTL 0x08 /* Global Control Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
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#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
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#define OFFSET_THR 0x28 /* Transmit Holding register */
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#define OFFSET_RBR 0x2C /* Receive Buffer register */
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#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
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#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
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#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
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#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
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#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
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#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
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#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
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#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
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#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
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#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
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#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
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#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
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#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
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#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
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#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
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# define CONFIG_SERIAL_BFIN_CTSRTS
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# ifndef CONFIG_UART0_CTS_PIN
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# define CONFIG_UART0_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART0_RTS_PIN
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# define CONFIG_UART0_RTS_PIN -1
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# endif
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# ifndef CONFIG_UART1_CTS_PIN
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# define CONFIG_UART1_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART1_RTS_PIN
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# define CONFIG_UART1_RTS_PIN -1
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# endif
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#endif
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/*
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* The pin configuration is different from schematic
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*/
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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int tx_count;
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struct circ_buf rx_dma_buf;
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struct timer_list rx_dma_timer;
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int rx_dma_nrows;
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unsigned int tx_dma_channel;
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unsigned int rx_dma_channel;
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struct work_struct tx_dma_workqueue;
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#else
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struct work_struct cts_workqueue;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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int cts_pin;
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int rts_pin;
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#endif
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};
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struct bfin_serial_port bfin_serial_ports[NR_PORTS];
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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int uart_cts_pin;
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int uart_rts_pin;
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#endif
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};
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struct bfin_serial_res bfin_serial_resource[] = {
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#ifdef CONFIG_SERIAL_BFIN_UART0
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{
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0xFFC00400,
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IRQ_UART0_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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#endif
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#ifdef CONFIG_BFIN_UART0_CTSRTS
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CONFIG_UART0_CTS_PIN,
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CONFIG_UART0_RTS_PIN,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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{
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0xFFC02000,
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IRQ_UART1_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART2
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{
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0xFFC02100,
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IRQ_UART2_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART2_TX,
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CH_UART2_RX,
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#endif
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#ifdef CONFIG_BFIN_UART2_CTSRTS
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CONFIG_UART2_CTS_PIN,
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CONFIG_UART2_RTS_PIN,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART3
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{
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0xFFC03100,
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IRQ_UART3_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART3_TX,
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CH_UART3_RX,
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#endif
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},
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#endif
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};
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int nr_ports = ARRAY_SIZE(bfin_serial_resource);
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static void bfin_serial_hw_init(struct bfin_serial_port *uart)
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{
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#ifdef CONFIG_SERIAL_BFIN_UART0
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/* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
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bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
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bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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/* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
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bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
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bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
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#ifdef CONFIG_BFIN_UART1_CTSRTS
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/* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
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bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
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bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
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#endif
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART2
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/* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
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bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART3
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/* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
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bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
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#ifdef CONFIG_BFIN_UART3_CTSRTS
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/* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
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bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
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#endif
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#endif
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SSYNC();
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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if (uart->cts_pin >= 0) {
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gpio_request(uart->cts_pin, NULL);
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gpio_direction_input(uart->cts_pin);
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}
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if (uart->rts_pin >= 0) {
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gpio_request(uart->rts_pin, NULL);
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gpio_direction_output(uart->rts_pin);
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}
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#endif
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}
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