OpenCloudOS-Kernel/drivers/clk/ti
Linus Torvalds ddebe839c6 This merge window we have one small clk provider API in the core framework and
then a bunch of driver updates and a handful of new drivers. In terms of
 diffstat the Qualcomm and Amlogic drivers are high up there because of all the
 clk data introcued by new drivers. The Nvidia Tegra driver had a lot of work
 done this cycle too to support suspend/resume and memory controllers. And the
 OMAP clk driver got proper clk and reset handling in place.
 
 Rounding out the patches are various updates to remove unused data, mark things
 static, correct incorrect data in drivers, etc. All the little things that
 improve drivers and maintain code health. I will point out that there's a patch
 in here for the GPIO clk driver, that almost nobody uses, which changes
 behavior and causes clk_set_rate() to try to change the GPIO gate clk's parent.
 Other than that things are fairly well SoC specific here.
 
 Core:
  - Add a clk provider API to get current parent index
  - Plug a memory leak in clk_unregister() path
 
 New Drivers:
  - CGU in Ingenix X1000
  - Bitmain BM1880 clks
  - Qualcomm MSM8998 GPU clk controllers
  - Qualcomm SC7180 GCC and RPMH clk controllers
  - Qualcomm QCS404 Q6SSTOP clk controllers
  - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC
  - Add support for the Renesas RZ/G2N (r8a774b1) SoC
  - Add Tegra20/30 External Memory Clock (EMC) support
 
 Updates:
  - Make gpio gate clks propagate rate setting up to parent
  - Prepare Armada 3700 for suspend to RAM by moving PCIe suspend/resume priority
  - Drop unused variables, enums, etc. in various clk drivers
  - Convert various drivers to use devm_platform_ioremap_resource()
  - Use struct_size() some more in various clk drivers
  - Improve Rockchip px30 clk tree
  - Add suspend/resume support to Tegra210 clk driver
  - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP
  - Allwinner DT exports and H6 clk tree fixes
  - Proper clk and reset handling for OMAP SoCs
  - Revamped TI divider clk to clamp max divider
  - Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs
  - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used
  - Add VIDEO2_PLL clock for imx8mq
  - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
  - Add sm1 support in the Amlogic audio clock controller
  - Switch some clocks on R-Car Gen2/3 to .determine_rate()
  - Remove Renesas R-Car Gen2 legacy DT clock support
  - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3
  - Improve Renesas R-Car Gen3 SD clock handling
  - Add rate table for Samsung exynos542x GPU and VPLL clks
  - Fix potential CPU performance degradation after system suspend/resume cycle
    on exynos542x SoCs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This merge window we have one small clk provider API in the core
  framework and then a bunch of driver updates and a handful of new
  drivers. In terms of diffstat the Qualcomm and Amlogic drivers are
  high up there because of all the clk data introcued by new drivers.
  The Nvidia Tegra driver had a lot of work done this cycle too to
  support suspend/resume and memory controllers. And the OMAP clk driver
  got proper clk and reset handling in place.

  Rounding out the patches are various updates to remove unused data,
  mark things static, correct incorrect data in drivers, etc. All the
  little things that improve drivers and maintain code health. I will
  point out that there's a patch in here for the GPIO clk driver, that
  almost nobody uses, which changes behavior and causes clk_set_rate()
  to try to change the GPIO gate clk's parent. Other than that things
  are fairly well SoC specific here.

  Core:
   - Add a clk provider API to get current parent index
   - Plug a memory leak in clk_unregister() path

  New Drivers:
   - CGU in Ingenix X1000
   - Bitmain BM1880 clks
   - Qualcomm MSM8998 GPU clk controllers
   - Qualcomm SC7180 GCC and RPMH clk controllers
   - Qualcomm QCS404 Q6SSTOP clk controllers
   - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC
   - Add support for the Renesas RZ/G2N (r8a774b1) SoC
   - Add Tegra20/30 External Memory Clock (EMC) support

  Updates:
   - Make gpio gate clks propagate rate setting up to parent
   - Prepare Armada 3700 for suspend to RAM by moving PCIe
     suspend/resume priority
   - Drop unused variables, enums, etc. in various clk drivers
   - Convert various drivers to use devm_platform_ioremap_resource()
   - Use struct_size() some more in various clk drivers
   - Improve Rockchip px30 clk tree
   - Add suspend/resume support to Tegra210 clk driver
   - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP
   - Allwinner DT exports and H6 clk tree fixes
   - Proper clk and reset handling for OMAP SoCs
   - Revamped TI divider clk to clamp max divider
   - Make 1443X/1416X PLL clock structure common for reusing among i.MX8
     SoCs
   - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used
   - Add VIDEO2_PLL clock for imx8mq
   - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
   - Add sm1 support in the Amlogic audio clock controller
   - Switch some clocks on R-Car Gen2/3 to .determine_rate()
   - Remove Renesas R-Car Gen2 legacy DT clock support
   - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3
   - Improve Renesas R-Car Gen3 SD clock handling
   - Add rate table for Samsung exynos542x GPU and VPLL clks
   - Fix potential CPU performance degradation after system
     suspend/resume cycle on exynos542x SoCs"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits)
  clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
  MAINTAINERS: Add entry for BM1880 SoC clock driver
  clk: Add common clock driver for BM1880 SoC
  dt-bindings: clock: Add devicetree binding for BM1880 SoC
  clk: Add clk_hw_unregister_composite helper function definition
  clk: Zero init clk_init_data in helpers
  clk: ingenic: Allow drivers to be built with COMPILE_TEST
  MAINTAINERS: Update section for Ux500 clock drivers
  clk: mark clk_disable_unused() as __init
  clk: Fix memory leak in clk_unregister()
  clk: Ingenic: Add CGU driver for X1000.
  dt-bindings: clock: Add X1000 bindings.
  clk: tegra: Use match_string() helper to simplify the code
  clk: pxa: fix one of the pxa RTC clocks
  clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
  clk: armada-xp: remove unused code
  clk: tegra: Fix build error without CONFIG_PM_SLEEP
  clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
  clk: tegra: Optimize PLLX restore on Tegra20/30
  clk: tegra: Add suspend and resume support on Tegra210
  ...
2019-12-01 16:06:02 -08:00
..
Kconfig treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
Makefile clk: ti: dra7xx: rename existing clkctrl data as compat data 2018-10-03 15:02:27 +03:00
adpll.c clk/ti/adpll: allocate room for terminating null 2019-11-08 09:00:37 -08:00
apll.c clk: ti: Don't reference clk_init_data after registration 2019-08-16 10:22:46 -07:00
autoidle.c clk: ti: check clock type before doing autoidle ops 2019-02-15 16:47:55 +02:00
clk-2xxx.c Merge branch 'cleanup-clk-h-includes' into clk-next 2015-07-28 11:59:09 -07:00
clk-3xxx.c clk: ti: omap3: cleanup unnecessary clock aliases 2017-12-01 15:17:17 +02:00
clk-7xx-compat.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clk-7xx.c This merge window we have one small clk provider API in the core framework and 2019-12-01 16:06:02 -08:00
clk-33xx-compat.c clk: ti: am33xx: rename existing clkctrl data as compat data 2018-10-03 15:02:26 +03:00
clk-33xx.c clk: ti: am33xx: drop idlest polling from gfx clock 2019-10-31 15:18:29 +02:00
clk-43xx-compat.c clk: ti: am43xx: rename existing clkctrl data as compat data 2018-10-03 15:02:26 +03:00
clk-43xx.c clk: ti: am43xx: drop idlest polling from gfx clock 2019-10-31 15:18:29 +02:00
clk-44xx.c clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks 2019-10-31 15:18:29 +02:00
clk-54xx.c clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks 2019-10-31 15:18:29 +02:00
clk-814x.c clk: ti: dm814x: Add of_node_put() to prevent memory leak 2019-08-07 15:26:39 -07:00
clk-816x.c clk: ti: dm816: add clkctrl clock data 2017-12-01 15:18:06 +02:00
clk-dra7-atl.c clk: ti: dra7-atl-clock: Remove ti_clk_add_alias call 2019-11-04 09:56:11 -08:00
clk.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clkctrl.c This merge window we have one small clk provider API in the core framework and 2019-12-01 16:06:02 -08:00
clkt_dflt.c clk: ti: convert to use proper register definition for all accesses 2017-03-08 13:06:15 +02:00
clkt_dpll.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clkt_iclk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clock.h clk: ti: divider: convert to use min,max,mask instead of width 2019-10-31 15:32:36 +02:00
clockdomain.c clk: ti: remove usage of CLK_IS_BASIC 2019-02-15 16:46:22 +02:00
composite.c clk: Convert to using %pOFn instead of device_node.name 2018-08-30 09:50:20 -07:00
divider.c clk: ti: divider: convert to use min,max,mask instead of width 2019-10-31 15:32:36 +02:00
dpll.c Merge branches 'clk-renesas', 'clk-rockchip', 'clk-const' and 'clk-simplify' into clk-next 2019-09-19 15:31:41 -07:00
dpll3xxx.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
dpll44xx.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
fapll.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
fixed-factor.c clk: Convert to using %pOFn instead of device_node.name 2018-08-30 09:50:20 -07:00
gate.c clk: ti: Remove unused functions 2019-06-07 11:54:48 -07:00
interface.c clk: ti: generalize the init sequence of clk_hw_omap clocks 2019-02-15 16:46:22 +02:00
mux.c clk: ti: Remove unused functions 2019-06-07 11:54:48 -07:00