627 lines
15 KiB
C
627 lines
15 KiB
C
/*
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* USB block power/access management abstraction.
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*
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* Au1000+: The OHCI block control register is at the far end of the OHCI memory
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* area. Au1550 has OHCI on different base address. No need to handle
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* UDC here.
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* Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
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* as well as the PHY for EHCI and UDC.
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*
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/syscore_ops.h>
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#include <asm/cpu.h>
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#include <asm/mach-au1x00/au1000.h>
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/* control register offsets */
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#define AU1000_OHCICFG 0x7fffc
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#define AU1550_OHCICFG 0x07ffc
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#define AU1200_USBCFG 0x04
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/* Au1000 USB block config bits */
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#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
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#define USBHEN_CE (1 << 3) /* OHCI block clock enable */
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#define USBHEN_E (1 << 2) /* OHCI block enable */
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#define USBHEN_C (1 << 1) /* OHCI block coherency bit */
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#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
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/* Au1200 USB config bits */
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#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
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#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
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#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
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#define USBCFG_SSD (1 << 23) /* serial short detect en */
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#define USBCFG_PPE (1 << 19) /* HS PHY PLL */
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#define USBCFG_UCE (1 << 18) /* UDC clock enable */
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#define USBCFG_ECE (1 << 17) /* EHCI clock enable */
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#define USBCFG_OCE (1 << 16) /* OHCI clock enable */
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#define USBCFG_FLA(x) (((x) & 0x3f) << 8)
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#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
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#define USBCFG_GME (1 << 6) /* OTG mem access */
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#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
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#define USBCFG_DME (1 << 4) /* UDC mem enable */
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#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
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#define USBCFG_EME (1 << 2) /* EHCI mem enable */
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#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
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#define USBCFG_OME (1 << 0) /* OHCI mem enable */
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#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
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USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
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USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
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USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
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USBCFG_OME)
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/* Au1300 USB config registers */
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#define USB_DWC_CTRL1 0x00
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#define USB_DWC_CTRL2 0x04
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#define USB_VBUS_TIMER 0x10
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#define USB_SBUS_CTRL 0x14
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#define USB_MSR_ERR 0x18
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#define USB_DWC_CTRL3 0x1C
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#define USB_DWC_CTRL4 0x20
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#define USB_OTG_STATUS 0x28
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#define USB_DWC_CTRL5 0x2C
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#define USB_DWC_CTRL6 0x30
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#define USB_DWC_CTRL7 0x34
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#define USB_PHY_STATUS 0xC0
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#define USB_INT_STATUS 0xC4
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#define USB_INT_ENABLE 0xC8
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#define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */
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#define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
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#define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */
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#define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */
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#define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */
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#define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
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#define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19)
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#define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18)
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#define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17)
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#define USB_DWC_CTRL3_OTG0_CKEN (1 << 16)
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#define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
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#define USB_INTEN_FORCE 0x20
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#define USB_INTEN_PHY 0x10
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#define USB_INTEN_UDC 0x08
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#define USB_INTEN_EHCI 0x04
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#define USB_INTEN_OHCI1 0x02
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#define USB_INTEN_OHCI0 0x01
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static DEFINE_SPINLOCK(alchemy_usb_lock);
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static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
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{
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unsigned long r, s;
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r = __raw_readl(base + USB_DWC_CTRL2);
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s = __raw_readl(base + USB_DWC_CTRL3);
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s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
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USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
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if (enable) {
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/* simply enable all PHYs */
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r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
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USB_DWC_CTRL2_PHYRS;
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__raw_writel(r, base + USB_DWC_CTRL2);
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wmb();
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} else if (!s) {
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/* no USB block active, do disable all PHYs */
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r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
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USB_DWC_CTRL2_PHYRS);
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__raw_writel(r, base + USB_DWC_CTRL2);
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wmb();
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}
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}
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static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
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{
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unsigned long r;
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if (enable) {
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__raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
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r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
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: USB_DWC_CTRL3_OHCI1_CKEN;
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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__au1300_usb_phyctl(base, enable); /* power up the PHYs */
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r = __raw_readl(base + USB_INT_ENABLE);
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r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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/* reset the OHCI start clock bit */
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__raw_writel(0, base + USB_DWC_CTRL7);
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wmb();
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} else {
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r = __raw_readl(base + USB_INT_ENABLE);
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r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL3);
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r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
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: USB_DWC_CTRL3_OHCI1_CKEN);
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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__au1300_usb_phyctl(base, enable);
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}
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}
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static inline void __au1300_ehci_control(void __iomem *base, int enable)
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{
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unsigned long r;
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if (enable) {
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r = __raw_readl(base + USB_DWC_CTRL3);
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r |= USB_DWC_CTRL3_EHCI0_CKEN;
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL1);
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r |= USB_DWC_CTRL1_HSTRS;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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__au1300_usb_phyctl(base, enable);
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r = __raw_readl(base + USB_INT_ENABLE);
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r |= USB_INTEN_EHCI;
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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} else {
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r = __raw_readl(base + USB_INT_ENABLE);
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r &= ~USB_INTEN_EHCI;
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL1);
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r &= ~USB_DWC_CTRL1_HSTRS;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL3);
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r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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__au1300_usb_phyctl(base, enable);
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}
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}
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static inline void __au1300_udc_control(void __iomem *base, int enable)
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{
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unsigned long r;
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if (enable) {
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r = __raw_readl(base + USB_DWC_CTRL1);
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r |= USB_DWC_CTRL1_DCRS;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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__au1300_usb_phyctl(base, enable);
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r = __raw_readl(base + USB_INT_ENABLE);
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r |= USB_INTEN_UDC;
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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} else {
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r = __raw_readl(base + USB_INT_ENABLE);
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r &= ~USB_INTEN_UDC;
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__raw_writel(r, base + USB_INT_ENABLE);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL1);
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r &= ~USB_DWC_CTRL1_DCRS;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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__au1300_usb_phyctl(base, enable);
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}
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}
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static inline void __au1300_otg_control(void __iomem *base, int enable)
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{
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unsigned long r;
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if (enable) {
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r = __raw_readl(base + USB_DWC_CTRL3);
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r |= USB_DWC_CTRL3_OTG0_CKEN;
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL1);
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r &= ~USB_DWC_CTRL1_OTGD;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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__au1300_usb_phyctl(base, enable);
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} else {
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r = __raw_readl(base + USB_DWC_CTRL1);
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r |= USB_DWC_CTRL1_OTGD;
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__raw_writel(r, base + USB_DWC_CTRL1);
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wmb();
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r = __raw_readl(base + USB_DWC_CTRL3);
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r &= ~USB_DWC_CTRL3_OTG0_CKEN;
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__raw_writel(r, base + USB_DWC_CTRL3);
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wmb();
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__au1300_usb_phyctl(base, enable);
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}
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}
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static inline int au1300_usb_control(int block, int enable)
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
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int ret = 0;
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switch (block) {
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case ALCHEMY_USB_OHCI0:
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__au1300_ohci_control(base, enable, 0);
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break;
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case ALCHEMY_USB_OHCI1:
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__au1300_ohci_control(base, enable, 1);
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break;
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case ALCHEMY_USB_EHCI0:
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__au1300_ehci_control(base, enable);
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break;
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case ALCHEMY_USB_UDC0:
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__au1300_udc_control(base, enable);
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break;
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case ALCHEMY_USB_OTG0:
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__au1300_otg_control(base, enable);
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break;
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default:
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ret = -ENODEV;
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}
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return ret;
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}
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static inline void au1300_usb_init(void)
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
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/* set some sane defaults. Note: we don't fiddle with DWC_CTRL4
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* here at all: Port 2 routing (EHCI or UDC) must be set either
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* by boot firmware or platform init code; I can't autodetect
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* a sane setting.
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*/
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__raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
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wmb();
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__raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
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wmb();
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__raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
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wmb();
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__raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
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wmb();
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/* set coherent access bit */
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__raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
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wmb();
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}
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static inline void __au1200_ohci_control(void __iomem *base, int enable)
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{
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unsigned long r = __raw_readl(base + AU1200_USBCFG);
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if (enable) {
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__raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
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wmb();
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udelay(2000);
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} else {
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__raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
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wmb();
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udelay(1000);
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}
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}
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static inline void __au1200_ehci_control(void __iomem *base, int enable)
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{
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unsigned long r = __raw_readl(base + AU1200_USBCFG);
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if (enable) {
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__raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
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wmb();
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udelay(1000);
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} else {
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if (!(r & USBCFG_UCE)) /* UDC also off? */
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r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
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__raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
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wmb();
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udelay(1000);
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}
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}
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static inline void __au1200_udc_control(void __iomem *base, int enable)
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{
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unsigned long r = __raw_readl(base + AU1200_USBCFG);
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if (enable) {
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__raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
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wmb();
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} else {
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if (!(r & USBCFG_ECE)) /* EHCI also off? */
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r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
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__raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
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wmb();
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}
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}
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static inline int au1200_usb_control(int block, int enable)
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
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switch (block) {
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case ALCHEMY_USB_OHCI0:
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__au1200_ohci_control(base, enable);
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break;
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case ALCHEMY_USB_UDC0:
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__au1200_udc_control(base, enable);
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break;
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case ALCHEMY_USB_EHCI0:
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__au1200_ehci_control(base, enable);
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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/* initialize USB block(s) to a known working state */
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static inline void au1200_usb_init(void)
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
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__raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
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wmb();
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udelay(1000);
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}
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static inline int au1000_usb_init(unsigned long rb, int reg)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
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unsigned long r = __raw_readl(base);
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struct clk *c;
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/* 48MHz check. Don't init if no one can provide it */
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c = clk_get(NULL, "usbh_clk");
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if (IS_ERR(c))
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return -ENODEV;
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if (clk_round_rate(c, 48000000) != 48000000) {
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clk_put(c);
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return -ENODEV;
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}
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if (clk_set_rate(c, 48000000)) {
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clk_put(c);
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return -ENODEV;
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}
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clk_put(c);
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#if defined(__BIG_ENDIAN)
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r |= USBHEN_BE;
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#endif
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r |= USBHEN_C;
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__raw_writel(r, base);
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wmb();
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udelay(1000);
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return 0;
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}
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static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
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unsigned long r = __raw_readl(base + creg);
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struct clk *c = clk_get(NULL, "usbh_clk");
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if (IS_ERR(c))
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return;
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if (enable) {
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if (clk_prepare_enable(c))
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goto out;
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__raw_writel(r | USBHEN_CE, base + creg);
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wmb();
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udelay(1000);
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__raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
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wmb();
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udelay(1000);
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/* wait for reset complete (read reg twice: au1500 erratum) */
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while (__raw_readl(base + creg),
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!(__raw_readl(base + creg) & USBHEN_RD))
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udelay(1000);
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} else {
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__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
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wmb();
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clk_disable_unprepare(c);
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}
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out:
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clk_put(c);
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}
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static inline int au1000_usb_control(int block, int enable, unsigned long rb,
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int creg)
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{
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int ret = 0;
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switch (block) {
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case ALCHEMY_USB_OHCI0:
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__au1xx0_ohci_control(enable, rb, creg);
|
|
break;
|
|
default:
|
|
ret = -ENODEV;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* alchemy_usb_control - control Alchemy on-chip USB blocks
|
|
* @block: USB block to target
|
|
* @enable: set 1 to enable a block, 0 to disable
|
|
*/
|
|
int alchemy_usb_control(int block, int enable)
|
|
{
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&alchemy_usb_lock, flags);
|
|
switch (alchemy_get_cputype()) {
|
|
case ALCHEMY_CPU_AU1000:
|
|
case ALCHEMY_CPU_AU1500:
|
|
case ALCHEMY_CPU_AU1100:
|
|
ret = au1000_usb_control(block, enable,
|
|
AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
|
|
break;
|
|
case ALCHEMY_CPU_AU1550:
|
|
ret = au1000_usb_control(block, enable,
|
|
AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
|
|
break;
|
|
case ALCHEMY_CPU_AU1200:
|
|
ret = au1200_usb_control(block, enable);
|
|
break;
|
|
case ALCHEMY_CPU_AU1300:
|
|
ret = au1300_usb_control(block, enable);
|
|
break;
|
|
default:
|
|
ret = -ENODEV;
|
|
}
|
|
spin_unlock_irqrestore(&alchemy_usb_lock, flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(alchemy_usb_control);
|
|
|
|
|
|
static unsigned long alchemy_usb_pmdata[2];
|
|
|
|
static void au1000_usb_pm(unsigned long br, int creg, int susp)
|
|
{
|
|
void __iomem *base = (void __iomem *)KSEG1ADDR(br);
|
|
|
|
if (susp) {
|
|
alchemy_usb_pmdata[0] = __raw_readl(base + creg);
|
|
/* There appears to be some undocumented reset register.... */
|
|
__raw_writel(0, base + 0x04);
|
|
wmb();
|
|
__raw_writel(0, base + creg);
|
|
wmb();
|
|
} else {
|
|
__raw_writel(alchemy_usb_pmdata[0], base + creg);
|
|
wmb();
|
|
}
|
|
}
|
|
|
|
static void au1200_usb_pm(int susp)
|
|
{
|
|
void __iomem *base =
|
|
(void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
|
|
if (susp) {
|
|
/* save OTG_CAP/MUX registers which indicate port routing */
|
|
/* FIXME: write an OTG driver to do that */
|
|
alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
|
|
alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
|
|
} else {
|
|
/* restore access to all MMIO areas */
|
|
au1200_usb_init();
|
|
|
|
/* restore OTG_CAP/MUX registers */
|
|
__raw_writel(alchemy_usb_pmdata[0], base + 0x00);
|
|
__raw_writel(alchemy_usb_pmdata[1], base + 0x04);
|
|
wmb();
|
|
}
|
|
}
|
|
|
|
static void au1300_usb_pm(int susp)
|
|
{
|
|
void __iomem *base =
|
|
(void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
|
|
/* remember Port2 routing */
|
|
if (susp) {
|
|
alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
|
|
} else {
|
|
au1300_usb_init();
|
|
__raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
|
|
wmb();
|
|
}
|
|
}
|
|
|
|
static void alchemy_usb_pm(int susp)
|
|
{
|
|
switch (alchemy_get_cputype()) {
|
|
case ALCHEMY_CPU_AU1000:
|
|
case ALCHEMY_CPU_AU1500:
|
|
case ALCHEMY_CPU_AU1100:
|
|
au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
|
|
break;
|
|
case ALCHEMY_CPU_AU1550:
|
|
au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
|
|
break;
|
|
case ALCHEMY_CPU_AU1200:
|
|
au1200_usb_pm(susp);
|
|
break;
|
|
case ALCHEMY_CPU_AU1300:
|
|
au1300_usb_pm(susp);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int alchemy_usb_suspend(void)
|
|
{
|
|
alchemy_usb_pm(1);
|
|
return 0;
|
|
}
|
|
|
|
static void alchemy_usb_resume(void)
|
|
{
|
|
alchemy_usb_pm(0);
|
|
}
|
|
|
|
static struct syscore_ops alchemy_usb_pm_ops = {
|
|
.suspend = alchemy_usb_suspend,
|
|
.resume = alchemy_usb_resume,
|
|
};
|
|
|
|
static int __init alchemy_usb_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (alchemy_get_cputype()) {
|
|
case ALCHEMY_CPU_AU1000:
|
|
case ALCHEMY_CPU_AU1500:
|
|
case ALCHEMY_CPU_AU1100:
|
|
ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
|
|
AU1000_OHCICFG);
|
|
break;
|
|
case ALCHEMY_CPU_AU1550:
|
|
ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
|
|
AU1550_OHCICFG);
|
|
break;
|
|
case ALCHEMY_CPU_AU1200:
|
|
au1200_usb_init();
|
|
break;
|
|
case ALCHEMY_CPU_AU1300:
|
|
au1300_usb_init();
|
|
break;
|
|
}
|
|
|
|
if (!ret)
|
|
register_syscore_ops(&alchemy_usb_pm_ops);
|
|
|
|
return ret;
|
|
}
|
|
arch_initcall(alchemy_usb_init);
|