171 lines
4.9 KiB
C
171 lines
4.9 KiB
C
/*
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* Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
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*
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* Previous incarnations were:
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* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
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* Copied and modified Carsten Langgaard's time.c
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
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* databooks). Firmware/Board init code must enable the counters in the
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* counter control register, otherwise the CP0 counter clocksource/event
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* will be installed instead (and use of 'wait' instruction is prohibited).
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*/
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/idle.h>
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#include <asm/processor.h>
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#include <asm/time.h>
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#include <asm/mach-au1x00/au1000.h>
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/* 32kHz clock enabled and detected */
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#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
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static cycle_t au1x_counter1_read(struct clocksource *cs)
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{
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return alchemy_rdsys(AU1000_SYS_RTCREAD);
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}
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static struct clocksource au1x_counter1_clocksource = {
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.name = "alchemy-counter1",
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.read = au1x_counter1_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.rating = 1500,
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};
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static int au1x_rtcmatch2_set_next_event(unsigned long delta,
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struct clock_event_device *cd)
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{
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delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
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/* wait for register access */
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while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
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;
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alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
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return 0;
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}
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static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
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{
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struct clock_event_device *cd = dev_id;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct clock_event_device au1x_rtcmatch2_clockdev = {
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.name = "rtcmatch2",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 1500,
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.set_next_event = au1x_rtcmatch2_set_next_event,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction au1x_rtcmatch2_irqaction = {
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.handler = au1x_rtcmatch2_irq,
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.flags = IRQF_TIMER,
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.name = "timer",
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.dev_id = &au1x_rtcmatch2_clockdev,
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};
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static int __init alchemy_time_init(unsigned int m2int)
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{
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struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
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unsigned long t;
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au1x_rtcmatch2_clockdev.irq = m2int;
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/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
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* has been detected. If so install the rtcmatch2 clocksource,
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* otherwise don't bother. Note that both bits being set is by
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* no means a definite guarantee that the counters actually work
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* (the 32S bit seems to be stuck set to 1 once a single clock-
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* edge is detected, hence the timeouts).
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*/
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if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
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goto cntr_err;
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/*
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* setup counter 1 (RTC) to tick at full speed
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*/
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t = 0xffffff;
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while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
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asm volatile ("nop");
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if (!t)
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goto cntr_err;
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alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */
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t = 0xffffff;
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while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
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asm volatile ("nop");
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if (!t)
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goto cntr_err;
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alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
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t = 0xffffff;
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while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
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asm volatile ("nop");
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if (!t)
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goto cntr_err;
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/* register counter1 clocksource and event device */
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clocksource_register_hz(&au1x_counter1_clocksource, 32768);
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cd->shift = 32;
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cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
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cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(9, cd); /* ~0.28ms */
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clockevents_register_device(cd);
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setup_irq(m2int, &au1x_rtcmatch2_irqaction);
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printk(KERN_INFO "Alchemy clocksource installed\n");
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return 0;
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cntr_err:
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return -1;
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}
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static int alchemy_m2inttab[] __initdata = {
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AU1000_RTC_MATCH2_INT,
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AU1500_RTC_MATCH2_INT,
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AU1100_RTC_MATCH2_INT,
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AU1550_RTC_MATCH2_INT,
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AU1200_RTC_MATCH2_INT,
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AU1300_RTC_MATCH2_INT,
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};
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void __init plat_time_init(void)
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{
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int t;
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t = alchemy_get_cputype();
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if (t == ALCHEMY_CPU_UNKNOWN ||
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alchemy_time_init(alchemy_m2inttab[t]))
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cpu_wait = NULL; /* wait doesn't work with r4k timer */
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}
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