153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2014-2016 IBM Corp.
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*/
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#include <linux/module.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include "pci.h"
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int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pnv_ioda_pe *pe;
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int rc;
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pe = pnv_ioda_get_pe(dev);
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if (!pe)
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return -ENODEV;
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pe_info(pe, "Switching PHB to CXL\n");
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rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
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if (rc == OPAL_UNSUPPORTED)
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dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
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else if (rc)
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dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
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return rc;
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}
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EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
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/* Find PHB for cxl dev and allocate MSI hwirqs?
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* Returns the absolute hardware IRQ number
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*/
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int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
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if (hwirq < 0) {
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dev_warn(&dev->dev, "Failed to find a free MSI\n");
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return -ENOSPC;
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}
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return phb->msi_base + hwirq;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
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void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq;
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for (i = 1; i < CXL_IRQ_RANGES; i++) {
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if (!irqs->range[i])
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continue;
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pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
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i, irqs->offset[i],
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irqs->range[i]);
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hwirq = irqs->offset[i] - phb->msi_base;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
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irqs->range[i]);
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}
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
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int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq, try;
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memset(irqs, 0, sizeof(struct cxl_irq_ranges));
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/* 0 is reserved for the multiplexed PSL DSI interrupt */
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for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
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try = num;
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while (try) {
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hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
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if (hwirq >= 0)
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break;
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try /= 2;
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}
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if (!try)
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goto fail;
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irqs->offset[i] = phb->msi_base + hwirq;
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irqs->range[i] = try;
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pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
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i, irqs->offset[i], irqs->range[i]);
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num -= try;
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}
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if (num)
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goto fail;
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return 0;
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fail:
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pnv_cxl_release_hwirq_ranges(irqs, dev);
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return -ENOSPC;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
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int pnv_cxl_get_irq_count(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return phb->msi_bmp.irq_count;
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}
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EXPORT_SYMBOL(pnv_cxl_get_irq_count);
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int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
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unsigned int virq)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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unsigned int xive_num = hwirq - phb->msi_base;
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struct pnv_ioda_pe *pe;
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int rc;
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if (!(pe = pnv_ioda_get_pe(dev)))
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return -ENODEV;
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/* Assign XIVE to PE */
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rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
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if (rc) {
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pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
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"hwirq 0x%x XIVE 0x%x PE\n",
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pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
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return -EIO;
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}
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pnv_set_msi_irq_chip(phb, virq);
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return 0;
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}
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EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
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