600 lines
15 KiB
C
600 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2017 IBM Corp.
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#include <asm/pnv-ocxl.h>
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#include <asm/opal.h>
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#include <misc/ocxl-config.h>
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#include "pci.h"
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#define PNV_OCXL_TL_P9_RECV_CAP 0x000000000000000Full
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#define PNV_OCXL_ACTAG_MAX 64
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/* PASIDs are 20-bit, but on P9, NPU can only handle 15 bits */
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#define PNV_OCXL_PASID_BITS 15
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#define PNV_OCXL_PASID_MAX ((1 << PNV_OCXL_PASID_BITS) - 1)
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#define AFU_PRESENT (1 << 31)
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#define AFU_INDEX_MASK 0x3F000000
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#define AFU_INDEX_SHIFT 24
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#define ACTAG_MASK 0xFFF
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struct actag_range {
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u16 start;
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u16 count;
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};
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struct npu_link {
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struct list_head list;
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int domain;
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int bus;
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int dev;
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u16 fn_desired_actags[8];
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struct actag_range fn_actags[8];
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bool assignment_done;
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};
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static struct list_head links_list = LIST_HEAD_INIT(links_list);
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static DEFINE_MUTEX(links_list_lock);
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/*
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* opencapi actags handling:
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*
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* When sending commands, the opencapi device references the memory
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* context it's targeting with an 'actag', which is really an alias
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* for a (BDF, pasid) combination. When it receives a command, the NPU
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* must do a lookup of the actag to identify the memory context. The
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* hardware supports a finite number of actags per link (64 for
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* POWER9).
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*
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* The device can carry multiple functions, and each function can have
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* multiple AFUs. Each AFU advertises in its config space the number
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* of desired actags. The host must configure in the config space of
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* the AFU how many actags the AFU is really allowed to use (which can
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* be less than what the AFU desires).
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*
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* When a PCI function is probed by the driver, it has no visibility
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* about the other PCI functions and how many actags they'd like,
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* which makes it impossible to distribute actags fairly among AFUs.
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*
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* Unfortunately, the only way to know how many actags a function
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* desires is by looking at the data for each AFU in the config space
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* and add them up. Similarly, the only way to know how many actags
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* all the functions of the physical device desire is by adding the
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* previously computed function counts. Then we can match that against
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* what the hardware supports.
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*
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* To get a comprehensive view, we use a 'pci fixup': at the end of
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* PCI enumeration, each function counts how many actags its AFUs
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* desire and we save it in a 'npu_link' structure, shared between all
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* the PCI functions of a same device. Therefore, when the first
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* function is probed by the driver, we can get an idea of the total
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* count of desired actags for the device, and assign the actags to
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* the AFUs, by pro-rating if needed.
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*/
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static int find_dvsec_from_pos(struct pci_dev *dev, int dvsec_id, int pos)
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{
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int vsec = pos;
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u16 vendor, id;
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while ((vsec = pci_find_next_ext_capability(dev, vsec,
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OCXL_EXT_CAP_ID_DVSEC))) {
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pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
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&vendor);
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pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
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if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
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return vsec;
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}
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return 0;
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}
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static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
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{
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int vsec = 0;
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u8 idx;
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while ((vsec = find_dvsec_from_pos(dev, OCXL_DVSEC_AFU_CTRL_ID,
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vsec))) {
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pci_read_config_byte(dev, vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
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&idx);
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if (idx == afu_idx)
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return vsec;
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}
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return 0;
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}
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static int get_max_afu_index(struct pci_dev *dev, int *afu_idx)
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{
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int pos;
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u32 val;
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pos = find_dvsec_from_pos(dev, OCXL_DVSEC_FUNC_ID, 0);
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if (!pos)
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return -ESRCH;
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pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
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if (val & AFU_PRESENT)
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*afu_idx = (val & AFU_INDEX_MASK) >> AFU_INDEX_SHIFT;
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else
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*afu_idx = -1;
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return 0;
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}
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static int get_actag_count(struct pci_dev *dev, int afu_idx, int *actag)
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{
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int pos;
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u16 actag_sup;
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pos = find_dvsec_afu_ctrl(dev, afu_idx);
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if (!pos)
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return -ESRCH;
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pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP,
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&actag_sup);
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*actag = actag_sup & ACTAG_MASK;
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return 0;
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}
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static struct npu_link *find_link(struct pci_dev *dev)
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{
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struct npu_link *link;
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list_for_each_entry(link, &links_list, list) {
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/* The functions of a device all share the same link */
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if (link->domain == pci_domain_nr(dev->bus) &&
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link->bus == dev->bus->number &&
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link->dev == PCI_SLOT(dev->devfn)) {
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return link;
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}
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}
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/* link doesn't exist yet. Allocate one */
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link = kzalloc(sizeof(struct npu_link), GFP_KERNEL);
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if (!link)
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return NULL;
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link->domain = pci_domain_nr(dev->bus);
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link->bus = dev->bus->number;
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link->dev = PCI_SLOT(dev->devfn);
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list_add(&link->list, &links_list);
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return link;
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}
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static void pnv_ocxl_fixup_actag(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct npu_link *link;
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int rc, afu_idx = -1, i, actag;
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if (!machine_is(powernv))
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return;
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if (phb->type != PNV_PHB_NPU_OCAPI)
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return;
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_warn(&dev->dev, "couldn't update actag information\n");
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mutex_unlock(&links_list_lock);
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return;
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}
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/*
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* Check how many actags are desired for the AFUs under that
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* function and add it to the count for the link
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*/
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rc = get_max_afu_index(dev, &afu_idx);
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if (rc) {
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/* Most likely an invalid config space */
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dev_dbg(&dev->dev, "couldn't find AFU information\n");
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afu_idx = -1;
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}
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link->fn_desired_actags[PCI_FUNC(dev->devfn)] = 0;
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for (i = 0; i <= afu_idx; i++) {
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/*
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* AFU index 'holes' are allowed. So don't fail if we
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* can't read the actag info for an index
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*/
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rc = get_actag_count(dev, i, &actag);
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if (rc)
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continue;
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link->fn_desired_actags[PCI_FUNC(dev->devfn)] += actag;
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}
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dev_dbg(&dev->dev, "total actags for function: %d\n",
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link->fn_desired_actags[PCI_FUNC(dev->devfn)]);
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mutex_unlock(&links_list_lock);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_ocxl_fixup_actag);
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static u16 assign_fn_actags(u16 desired, u16 total)
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{
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u16 count;
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if (total <= PNV_OCXL_ACTAG_MAX)
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count = desired;
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else
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count = PNV_OCXL_ACTAG_MAX * desired / total;
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return count;
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}
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static void assign_actags(struct npu_link *link)
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{
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u16 actag_count, range_start = 0, total_desired = 0;
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int i;
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for (i = 0; i < 8; i++)
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total_desired += link->fn_desired_actags[i];
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for (i = 0; i < 8; i++) {
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if (link->fn_desired_actags[i]) {
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actag_count = assign_fn_actags(
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link->fn_desired_actags[i],
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total_desired);
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link->fn_actags[i].start = range_start;
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link->fn_actags[i].count = actag_count;
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range_start += actag_count;
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WARN_ON(range_start >= PNV_OCXL_ACTAG_MAX);
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}
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pr_debug("link %x:%x:%x fct %d actags: start=%d count=%d (desired=%d)\n",
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link->domain, link->bus, link->dev, i,
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link->fn_actags[i].start, link->fn_actags[i].count,
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link->fn_desired_actags[i]);
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}
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link->assignment_done = true;
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}
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int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled,
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u16 *supported)
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{
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struct npu_link *link;
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_err(&dev->dev, "actag information not found\n");
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mutex_unlock(&links_list_lock);
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return -ENODEV;
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}
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/*
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* On p9, we only have 64 actags per link, so they must be
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* shared by all the functions of the same adapter. We counted
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* the desired actag counts during PCI enumeration, so that we
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* can allocate a pro-rated number of actags to each function.
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*/
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if (!link->assignment_done)
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assign_actags(link);
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*base = link->fn_actags[PCI_FUNC(dev->devfn)].start;
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*enabled = link->fn_actags[PCI_FUNC(dev->devfn)].count;
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*supported = link->fn_desired_actags[PCI_FUNC(dev->devfn)];
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mutex_unlock(&links_list_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_actag);
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int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count)
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{
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struct npu_link *link;
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int i, rc = -EINVAL;
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/*
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* The number of PASIDs (process address space ID) which can
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* be used by a function depends on how many functions exist
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* on the device. The NPU needs to be configured to know how
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* many bits are available to PASIDs and how many are to be
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* used by the function BDF indentifier.
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*
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* We only support one AFU-carrying function for now.
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*/
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mutex_lock(&links_list_lock);
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link = find_link(dev);
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if (!link) {
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dev_err(&dev->dev, "actag information not found\n");
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mutex_unlock(&links_list_lock);
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return -ENODEV;
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}
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for (i = 0; i < 8; i++)
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if (link->fn_desired_actags[i] && (i == PCI_FUNC(dev->devfn))) {
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*count = PNV_OCXL_PASID_MAX;
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rc = 0;
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break;
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}
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mutex_unlock(&links_list_lock);
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dev_dbg(&dev->dev, "%d PASIDs available for function\n",
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rc ? 0 : *count);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_pasid_count);
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static void set_templ_rate(unsigned int templ, unsigned int rate, char *buf)
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{
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int shift, idx;
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WARN_ON(templ > PNV_OCXL_TL_MAX_TEMPLATE);
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idx = (PNV_OCXL_TL_MAX_TEMPLATE - templ) / 2;
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shift = 4 * (1 - ((PNV_OCXL_TL_MAX_TEMPLATE - templ) % 2));
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buf[idx] |= rate << shift;
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}
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int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
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char *rate_buf, int rate_buf_size)
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{
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if (rate_buf_size != PNV_OCXL_TL_RATE_BUF_SIZE)
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return -EINVAL;
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/*
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* The TL capabilities are a characteristic of the NPU, so
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* we go with hard-coded values.
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*
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* The receiving rate of each template is encoded on 4 bits.
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*
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* On P9:
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* - templates 0 -> 3 are supported
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* - templates 0, 1 and 3 have a 0 receiving rate
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* - template 2 has receiving rate of 1 (extra cycle)
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*/
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memset(rate_buf, 0, rate_buf_size);
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set_templ_rate(2, 1, rate_buf);
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*cap = PNV_OCXL_TL_P9_RECV_CAP;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_tl_cap);
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int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
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uint64_t rate_buf_phys, int rate_buf_size)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int rc;
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if (rate_buf_size != PNV_OCXL_TL_RATE_BUF_SIZE)
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return -EINVAL;
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rc = opal_npu_tl_set(phb->opal_id, dev->devfn, cap,
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rate_buf_phys, rate_buf_size);
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if (rc) {
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dev_err(&dev->dev, "Can't configure host TL: %d\n", rc);
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_set_tl_conf);
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int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq)
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{
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int rc;
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rc = of_property_read_u32(dev->dev.of_node, "ibm,opal-xsl-irq", hwirq);
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if (rc) {
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dev_err(&dev->dev,
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"Can't get translation interrupt for device\n");
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return rc;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_get_xsl_irq);
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void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
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void __iomem *tfc, void __iomem *pe_handle)
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{
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iounmap(dsisr);
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iounmap(dar);
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iounmap(tfc);
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iounmap(pe_handle);
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_unmap_xsl_regs);
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int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
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void __iomem **dar, void __iomem **tfc,
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void __iomem **pe_handle)
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{
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u64 reg;
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int i, j, rc = 0;
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void __iomem *regs[4];
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/*
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* opal stores the mmio addresses of the DSISR, DAR, TFC and
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* PE_HANDLE registers in a device tree property, in that
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* order
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*/
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for (i = 0; i < 4; i++) {
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rc = of_property_read_u64_index(dev->dev.of_node,
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"ibm,opal-xsl-mmio", i, ®);
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if (rc)
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break;
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regs[i] = ioremap(reg, 8);
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if (!regs[i]) {
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rc = -EINVAL;
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break;
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}
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}
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if (rc) {
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dev_err(&dev->dev, "Can't map translation mmio registers\n");
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for (j = i - 1; j >= 0; j--)
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iounmap(regs[j]);
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} else {
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*dsisr = regs[0];
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*dar = regs[1];
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*tfc = regs[2];
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*pe_handle = regs[3];
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}
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return rc;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_map_xsl_regs);
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struct spa_data {
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u64 phb_opal_id;
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u32 bdfn;
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};
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int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask,
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void **platform_data)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct spa_data *data;
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u32 bdfn;
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int rc;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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bdfn = (dev->bus->number << 8) | dev->devfn;
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rc = opal_npu_spa_setup(phb->opal_id, bdfn, virt_to_phys(spa_mem),
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PE_mask);
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if (rc) {
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dev_err(&dev->dev, "Can't setup Shared Process Area: %d\n", rc);
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kfree(data);
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return rc;
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}
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data->phb_opal_id = phb->opal_id;
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data->bdfn = bdfn;
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*platform_data = (void *) data;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_spa_setup);
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void pnv_ocxl_spa_release(void *platform_data)
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{
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struct spa_data *data = (struct spa_data *) platform_data;
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int rc;
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rc = opal_npu_spa_setup(data->phb_opal_id, data->bdfn, 0, 0);
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WARN_ON(rc);
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kfree(data);
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release);
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int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle)
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{
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struct spa_data *data = (struct spa_data *) platform_data;
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int rc;
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rc = opal_npu_spa_clear_cache(data->phb_opal_id, data->bdfn, pe_handle);
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return rc;
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}
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EXPORT_SYMBOL_GPL(pnv_ocxl_spa_remove_pe_from_cache);
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int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
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uint64_t lpcr, void __iomem **arva)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(dev->bus);
|
|
struct pnv_phb *phb = hose->private_data;
|
|
u64 mmio_atsd;
|
|
int rc;
|
|
|
|
/* ATSD physical address.
|
|
* ATSD LAUNCH register: write access initiates a shoot down to
|
|
* initiate the TLB Invalidate command.
|
|
*/
|
|
rc = of_property_read_u64_index(hose->dn, "ibm,mmio-atsd",
|
|
0, &mmio_atsd);
|
|
if (rc) {
|
|
dev_info(&dev->dev, "No available ATSD found\n");
|
|
return rc;
|
|
}
|
|
|
|
/* Assign a register set to a Logical Partition and MMIO ATSD
|
|
* LPARID register to the required value.
|
|
*/
|
|
rc = opal_npu_map_lpar(phb->opal_id, pci_dev_id(dev),
|
|
lparid, lpcr);
|
|
if (rc) {
|
|
dev_err(&dev->dev, "Error mapping device to LPAR: %d\n", rc);
|
|
return rc;
|
|
}
|
|
|
|
*arva = ioremap(mmio_atsd, 24);
|
|
if (!(*arva)) {
|
|
dev_warn(&dev->dev, "ioremap failed - mmio_atsd: %#llx\n", mmio_atsd);
|
|
rc = -ENOMEM;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pnv_ocxl_map_lpar);
|
|
|
|
void pnv_ocxl_unmap_lpar(void __iomem *arva)
|
|
{
|
|
iounmap(arva);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pnv_ocxl_unmap_lpar);
|
|
|
|
void pnv_ocxl_tlb_invalidate(void __iomem *arva,
|
|
unsigned long pid,
|
|
unsigned long addr,
|
|
unsigned long page_size)
|
|
{
|
|
unsigned long timeout = jiffies + (HZ * PNV_OCXL_ATSD_TIMEOUT);
|
|
u64 val = 0ull;
|
|
int pend;
|
|
u8 size;
|
|
|
|
if (!(arva))
|
|
return;
|
|
|
|
if (addr) {
|
|
/* load Abbreviated Virtual Address register with
|
|
* the necessary value
|
|
*/
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_AVA_AVA, addr >> (63-51));
|
|
out_be64(arva + PNV_OCXL_ATSD_AVA, val);
|
|
}
|
|
|
|
/* Write access initiates a shoot down to initiate the
|
|
* TLB Invalidate command
|
|
*/
|
|
val = PNV_OCXL_ATSD_LNCH_R;
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_RIC, 0b10);
|
|
if (addr)
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_IS, 0b00);
|
|
else {
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_IS, 0b01);
|
|
val |= PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON;
|
|
}
|
|
val |= PNV_OCXL_ATSD_LNCH_PRS;
|
|
/* Actual Page Size to be invalidated
|
|
* 000 4KB
|
|
* 101 64KB
|
|
* 001 2MB
|
|
* 010 1GB
|
|
*/
|
|
size = 0b101;
|
|
if (page_size == 0x1000)
|
|
size = 0b000;
|
|
if (page_size == 0x200000)
|
|
size = 0b001;
|
|
if (page_size == 0x40000000)
|
|
size = 0b010;
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_AP, size);
|
|
val |= FIELD_PREP(PNV_OCXL_ATSD_LNCH_PID, pid);
|
|
out_be64(arva + PNV_OCXL_ATSD_LNCH, val);
|
|
|
|
/* Poll the ATSD status register to determine when the
|
|
* TLB Invalidate has been completed.
|
|
*/
|
|
val = in_be64(arva + PNV_OCXL_ATSD_STAT);
|
|
pend = val >> 63;
|
|
|
|
while (pend) {
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
pr_err("%s - Timeout while reading XTS MMIO ATSD status register (val=%#llx, pidr=0x%lx)\n",
|
|
__func__, val, pid);
|
|
return;
|
|
}
|
|
cpu_relax();
|
|
val = in_be64(arva + PNV_OCXL_ATSD_STAT);
|
|
pend = val >> 63;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(pnv_ocxl_tlb_invalidate);
|