374 lines
9.2 KiB
C
374 lines
9.2 KiB
C
/*
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* Library implementing the most common irq chip callback functions
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*
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* Copyright (C) 2011, Thomas Gleixner
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/syscore_ops.h>
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#include "internals.h"
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static LIST_HEAD(gc_list);
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static DEFINE_RAW_SPINLOCK(gc_lock);
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static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
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{
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return &container_of(d->chip, struct irq_chip_type, chip)->regs;
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}
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/**
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* irq_gc_noop - NOOP function
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* @d: irq_data
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*/
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void irq_gc_noop(struct irq_data *d)
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{
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}
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/**
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* irq_gc_mask_disable_reg - Mask chip via disable register
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* @d: irq_data
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*
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* Chip has separate enable/disable registers instead of a single mask
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* register.
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*/
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void irq_gc_mask_disable_reg(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
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gc->mask_cache &= ~mask;
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
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* @d: irq_data
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*
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* Chip has a single mask register. Values of this register are cached
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* and protected by gc->lock
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*/
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void irq_gc_mask_set_bit(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache |= mask;
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irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
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* @d: irq_data
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*
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* Chip has a single mask register. Values of this register are cached
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* and protected by gc->lock
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*/
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void irq_gc_mask_clr_bit(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache &= ~mask;
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irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_unmask_enable_reg - Unmask chip via enable register
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* @d: irq_data
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*
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* Chip has separate enable/disable registers instead of a single mask
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* register.
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*/
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void irq_gc_unmask_enable_reg(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
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gc->mask_cache |= mask;
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_ack_set_bit - Ack pending interrupt via setting bit
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* @d: irq_data
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*/
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void irq_gc_ack_set_bit(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
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* @d: irq_data
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*/
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void irq_gc_ack_clr_bit(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = ~(1 << (d->irq - gc->irq_base));
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
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* @d: irq_data
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*/
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void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_eoi - EOI interrupt
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* @d: irq_data
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*/
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void irq_gc_eoi(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
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irq_gc_unlock(gc);
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}
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/**
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* irq_gc_set_wake - Set/clr wake bit for an interrupt
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* @d: irq_data
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*
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* For chips where the wake from suspend functionality is not
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* configured in a separate register and the wakeup active state is
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* just stored in a bitmask.
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*/
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int irq_gc_set_wake(struct irq_data *d, unsigned int on)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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if (!(mask & gc->wake_enabled))
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return -EINVAL;
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irq_gc_lock(gc);
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if (on)
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gc->wake_active |= mask;
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else
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gc->wake_active &= ~mask;
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irq_gc_unlock(gc);
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return 0;
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}
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/**
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* irq_alloc_generic_chip - Allocate a generic chip and initialize it
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* @name: Name of the irq chip
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* @num_ct: Number of irq_chip_type instances associated with this
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* @irq_base: Interrupt base nr for this chip
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* @reg_base: Register base address (virtual)
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* @handler: Default flow handler associated with this chip
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*
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* Returns an initialized irq_chip_generic structure. The chip defaults
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* to the primary (index 0) irq_chip_type and @handler
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*/
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struct irq_chip_generic *
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irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
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void __iomem *reg_base, irq_flow_handler_t handler)
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{
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struct irq_chip_generic *gc;
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unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
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gc = kzalloc(sz, GFP_KERNEL);
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if (gc) {
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raw_spin_lock_init(&gc->lock);
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gc->num_ct = num_ct;
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gc->irq_base = irq_base;
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gc->reg_base = reg_base;
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gc->chip_types->chip.name = name;
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gc->chip_types->handler = handler;
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}
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return gc;
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}
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EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
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/*
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* Separate lockdep class for interrupt chip which can nest irq_desc
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* lock.
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*/
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static struct lock_class_key irq_nested_lock_class;
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/**
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* irq_setup_generic_chip - Setup a range of interrupts with a generic chip
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* @gc: Generic irq chip holding all data
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* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
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* @flags: Flags for initialization
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* @clr: IRQ_* bits to clear
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* @set: IRQ_* bits to set
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*
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* Set up max. 32 interrupts starting from gc->irq_base. Note, this
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* initializes all interrupts to the primary irq_chip_type and its
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* associated handler.
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*/
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void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
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enum irq_gc_flags flags, unsigned int clr,
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unsigned int set)
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{
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struct irq_chip_type *ct = gc->chip_types;
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unsigned int i;
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raw_spin_lock(&gc_lock);
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list_add_tail(&gc->list, &gc_list);
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raw_spin_unlock(&gc_lock);
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/* Init mask cache ? */
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if (flags & IRQ_GC_INIT_MASK_CACHE)
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gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
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for (i = gc->irq_base; msk; msk >>= 1, i++) {
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if (!(msk & 0x01))
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continue;
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if (flags & IRQ_GC_INIT_NESTED_LOCK)
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irq_set_lockdep_class(i, &irq_nested_lock_class);
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irq_set_chip_and_handler(i, &ct->chip, ct->handler);
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irq_set_chip_data(i, gc);
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irq_modify_status(i, clr, set);
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}
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gc->irq_cnt = i - gc->irq_base;
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}
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EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
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/**
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* irq_setup_alt_chip - Switch to alternative chip
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* @d: irq_data for this interrupt
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* @type Flow type to be initialized
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*
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* Only to be called from chip->irq_set_type() callbacks.
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*/
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int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = gc->chip_types;
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unsigned int i;
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for (i = 0; i < gc->num_ct; i++, ct++) {
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if (ct->type & type) {
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d->chip = &ct->chip;
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irq_data_to_desc(d)->handle_irq = ct->handler;
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return 0;
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}
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}
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
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/**
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* irq_remove_generic_chip - Remove a chip
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* @gc: Generic irq chip holding all data
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* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
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* @clr: IRQ_* bits to clear
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* @set: IRQ_* bits to set
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*
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* Remove up to 32 interrupts starting from gc->irq_base.
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*/
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void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
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unsigned int clr, unsigned int set)
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{
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unsigned int i = gc->irq_base;
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raw_spin_lock(&gc_lock);
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list_del(&gc->list);
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raw_spin_unlock(&gc_lock);
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for (; msk; msk >>= 1, i++) {
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if (!(msk & 0x01))
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continue;
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/* Remove handler first. That will mask the irq line */
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irq_set_handler(i, NULL);
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irq_set_chip(i, &no_irq_chip);
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irq_set_chip_data(i, NULL);
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irq_modify_status(i, clr, set);
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}
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}
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EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
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#ifdef CONFIG_PM
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static int irq_gc_suspend(void)
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{
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struct irq_chip_generic *gc;
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list_for_each_entry(gc, &gc_list, list) {
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struct irq_chip_type *ct = gc->chip_types;
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if (ct->chip.irq_suspend)
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ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
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}
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return 0;
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}
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static void irq_gc_resume(void)
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{
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struct irq_chip_generic *gc;
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list_for_each_entry(gc, &gc_list, list) {
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struct irq_chip_type *ct = gc->chip_types;
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if (ct->chip.irq_resume)
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ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
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}
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}
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#else
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#define irq_gc_suspend NULL
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#define irq_gc_resume NULL
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#endif
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static void irq_gc_shutdown(void)
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{
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struct irq_chip_generic *gc;
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list_for_each_entry(gc, &gc_list, list) {
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struct irq_chip_type *ct = gc->chip_types;
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if (ct->chip.irq_pm_shutdown)
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ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
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}
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}
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static struct syscore_ops irq_gc_syscore_ops = {
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.suspend = irq_gc_suspend,
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.resume = irq_gc_resume,
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.shutdown = irq_gc_shutdown,
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};
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static int __init irq_gc_init_ops(void)
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{
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register_syscore_ops(&irq_gc_syscore_ops);
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return 0;
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}
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device_initcall(irq_gc_init_ops);
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