486 lines
14 KiB
C
486 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Hantro VPU codec driver
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*
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* Copyright 2018 Google LLC.
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* Tomasz Figa <tfiga@chromium.org>
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*
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* Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
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* Copyright (C) 2011 Samsung Electronics Co., Ltd.
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*/
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#ifndef HANTRO_H_
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#define HANTRO_H_
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#include <linux/platform_device.h>
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#include <linux/videodev2.h>
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#include <linux/wait.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-mem2mem.h>
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#include <media/videobuf2-core.h>
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#include <media/videobuf2-dma-contig.h>
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#include "hantro_hw.h"
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struct hantro_ctx;
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struct hantro_codec_ops;
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struct hantro_postproc_ops;
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#define HANTRO_JPEG_ENCODER BIT(0)
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#define HANTRO_ENCODERS 0x0000ffff
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#define HANTRO_MPEG2_DECODER BIT(16)
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#define HANTRO_VP8_DECODER BIT(17)
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#define HANTRO_H264_DECODER BIT(18)
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#define HANTRO_HEVC_DECODER BIT(19)
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#define HANTRO_VP9_DECODER BIT(20)
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#define HANTRO_DECODERS 0xffff0000
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/**
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* struct hantro_irq - irq handler and name
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*
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* @name: irq name for device tree lookup
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* @handler: interrupt handler
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*/
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struct hantro_irq {
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const char *name;
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irqreturn_t (*handler)(int irq, void *priv);
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};
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/**
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* struct hantro_variant - information about VPU hardware variant
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*
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* @enc_offset: Offset from VPU base to encoder registers.
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* @dec_offset: Offset from VPU base to decoder registers.
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* @enc_fmts: Encoder formats.
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* @num_enc_fmts: Number of encoder formats.
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* @dec_fmts: Decoder formats.
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* @num_dec_fmts: Number of decoder formats.
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* @postproc_fmts: Post-processor formats.
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* @num_postproc_fmts: Number of post-processor formats.
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* @postproc_ops: Post-processor ops.
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* @codec: Supported codecs
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* @codec_ops: Codec ops.
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* @init: Initialize hardware, optional.
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* @runtime_resume: reenable hardware after power gating, optional.
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* @irqs: array of irq names and interrupt handlers
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* @num_irqs: number of irqs in the array
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* @clk_names: array of clock names
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* @num_clocks: number of clocks in the array
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* @reg_names: array of register range names
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* @num_regs: number of register range names in the array
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* @double_buffer: core needs double buffering
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* @legacy_regs: core uses legacy register set
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* @late_postproc: postproc must be set up at the end of the job
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*/
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struct hantro_variant {
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unsigned int enc_offset;
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unsigned int dec_offset;
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const struct hantro_fmt *enc_fmts;
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unsigned int num_enc_fmts;
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const struct hantro_fmt *dec_fmts;
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unsigned int num_dec_fmts;
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const struct hantro_fmt *postproc_fmts;
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unsigned int num_postproc_fmts;
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const struct hantro_postproc_ops *postproc_ops;
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unsigned int codec;
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const struct hantro_codec_ops *codec_ops;
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int (*init)(struct hantro_dev *vpu);
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int (*runtime_resume)(struct hantro_dev *vpu);
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const struct hantro_irq *irqs;
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int num_irqs;
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const char * const *clk_names;
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int num_clocks;
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const char * const *reg_names;
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int num_regs;
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unsigned int double_buffer : 1;
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unsigned int legacy_regs : 1;
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unsigned int late_postproc : 1;
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};
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/**
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* enum hantro_codec_mode - codec operating mode.
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* @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
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* @HANTRO_MODE_JPEG_ENC: JPEG encoder.
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* @HANTRO_MODE_H264_DEC: H264 decoder.
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* @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
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* @HANTRO_MODE_VP8_DEC: VP8 decoder.
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* @HANTRO_MODE_HEVC_DEC: HEVC decoder.
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* @HANTRO_MODE_VP9_DEC: VP9 decoder.
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*/
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enum hantro_codec_mode {
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HANTRO_MODE_NONE = -1,
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HANTRO_MODE_JPEG_ENC,
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HANTRO_MODE_H264_DEC,
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HANTRO_MODE_MPEG2_DEC,
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HANTRO_MODE_VP8_DEC,
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HANTRO_MODE_HEVC_DEC,
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HANTRO_MODE_VP9_DEC,
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};
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/*
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* struct hantro_ctrl - helper type to declare supported controls
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* @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
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* @cfg: control configuration
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*/
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struct hantro_ctrl {
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unsigned int codec;
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struct v4l2_ctrl_config cfg;
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};
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/*
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* struct hantro_func - Hantro VPU functionality
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*
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* @id: processing functionality ID (can be
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* %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
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* %MEDIA_ENT_F_PROC_VIDEO_DECODER)
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* @vdev: &struct video_device that exposes the encoder or
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* decoder functionality
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* @source_pad: &struct media_pad with the source pad.
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* @sink: &struct media_entity pointer with the sink entity
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* @sink_pad: &struct media_pad with the sink pad.
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* @proc: &struct media_entity pointer with the M2M device itself.
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* @proc_pads: &struct media_pad with the @proc pads.
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* @intf_devnode: &struct media_intf devnode pointer with the interface
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* with controls the M2M device.
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*
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* Contains everything needed to attach the video device to the media device.
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*/
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struct hantro_func {
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unsigned int id;
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struct video_device vdev;
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struct media_pad source_pad;
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struct media_entity sink;
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struct media_pad sink_pad;
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struct media_entity proc;
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struct media_pad proc_pads[2];
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struct media_intf_devnode *intf_devnode;
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};
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static inline struct hantro_func *
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hantro_vdev_to_func(struct video_device *vdev)
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{
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return container_of(vdev, struct hantro_func, vdev);
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}
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/**
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* struct hantro_dev - driver data
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* @v4l2_dev: V4L2 device to register video devices for.
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* @m2m_dev: mem2mem device associated to this device.
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* @mdev: media device associated to this device.
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* @encoder: encoder functionality.
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* @decoder: decoder functionality.
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* @pdev: Pointer to VPU platform device.
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* @dev: Pointer to device for convenient logging using
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* dev_ macros.
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* @clocks: Array of clock handles.
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* @resets: Array of reset handles.
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* @reg_bases: Mapped addresses of VPU registers.
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* @enc_base: Mapped address of VPU encoder register for convenience.
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* @dec_base: Mapped address of VPU decoder register for convenience.
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* @ctrl_base: Mapped address of VPU control block.
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* @vpu_mutex: Mutex to synchronize V4L2 calls.
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* @irqlock: Spinlock to synchronize access to data structures
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* shared with interrupt handlers.
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* @variant: Hardware variant-specific parameters.
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* @watchdog_work: Delayed work for hardware timeout handling.
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*/
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struct hantro_dev {
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struct v4l2_device v4l2_dev;
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struct v4l2_m2m_dev *m2m_dev;
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struct media_device mdev;
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struct hantro_func *encoder;
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struct hantro_func *decoder;
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struct platform_device *pdev;
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struct device *dev;
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struct clk_bulk_data *clocks;
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struct reset_control *resets;
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void __iomem **reg_bases;
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void __iomem *enc_base;
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void __iomem *dec_base;
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void __iomem *ctrl_base;
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struct mutex vpu_mutex; /* video_device lock */
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spinlock_t irqlock;
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const struct hantro_variant *variant;
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struct delayed_work watchdog_work;
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};
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/**
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* struct hantro_ctx - Context (instance) private data.
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*
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* @dev: VPU driver data to which the context belongs.
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* @fh: V4L2 file handler.
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* @is_encoder: Decoder or encoder context?
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*
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* @sequence_cap: Sequence counter for capture queue
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* @sequence_out: Sequence counter for output queue
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*
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* @vpu_src_fmt: Descriptor of active source format.
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* @src_fmt: V4L2 pixel format of active source format.
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* @vpu_dst_fmt: Descriptor of active destination format.
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* @dst_fmt: V4L2 pixel format of active destination format.
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*
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* @ctrl_handler: Control handler used to register controls.
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* @jpeg_quality: User-specified JPEG compression quality.
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* @bit_depth: Bit depth of current frame
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*
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* @codec_ops: Set of operations related to codec mode.
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* @postproc: Post-processing context.
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* @h264_dec: H.264-decoding context.
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* @jpeg_enc: JPEG-encoding context.
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* @mpeg2_dec: MPEG-2-decoding context.
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* @vp8_dec: VP8-decoding context.
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* @hevc_dec: HEVC-decoding context.
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* @vp9_dec: VP9-decoding context.
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*/
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struct hantro_ctx {
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struct hantro_dev *dev;
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struct v4l2_fh fh;
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bool is_encoder;
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u32 sequence_cap;
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u32 sequence_out;
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const struct hantro_fmt *vpu_src_fmt;
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struct v4l2_pix_format_mplane src_fmt;
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const struct hantro_fmt *vpu_dst_fmt;
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struct v4l2_pix_format_mplane dst_fmt;
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struct v4l2_ctrl_handler ctrl_handler;
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int jpeg_quality;
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int bit_depth;
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const struct hantro_codec_ops *codec_ops;
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struct hantro_postproc_ctx postproc;
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/* Specific for particular codec modes. */
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union {
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struct hantro_h264_dec_hw_ctx h264_dec;
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struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
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struct hantro_vp8_dec_hw_ctx vp8_dec;
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struct hantro_hevc_dec_hw_ctx hevc_dec;
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struct hantro_vp9_dec_hw_ctx vp9_dec;
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};
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};
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/**
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* struct hantro_fmt - information about supported video formats.
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* @name: Human readable name of the format.
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* @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
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* @codec_mode: Codec mode related to this format. See
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* enum hantro_codec_mode.
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* @header_size: Optional header size. Currently used by JPEG encoder.
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* @max_depth: Maximum depth, for bitstream formats
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* @enc_fmt: Format identifier for encoder registers.
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* @frmsize: Supported range of frame sizes (only for bitstream formats).
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* @postprocessed: Indicates if this format needs the post-processor.
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* @match_depth: Indicates if format bit depth must match video bit depth
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*/
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struct hantro_fmt {
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char *name;
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u32 fourcc;
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enum hantro_codec_mode codec_mode;
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int header_size;
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int max_depth;
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enum hantro_enc_fmt enc_fmt;
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struct v4l2_frmsize_stepwise frmsize;
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bool postprocessed;
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bool match_depth;
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};
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struct hantro_reg {
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u32 base;
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u32 shift;
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u32 mask;
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};
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struct hantro_postproc_regs {
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struct hantro_reg pipeline_en;
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struct hantro_reg max_burst;
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struct hantro_reg clk_gate;
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struct hantro_reg out_swap32;
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struct hantro_reg out_endian;
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struct hantro_reg out_luma_base;
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struct hantro_reg input_width;
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struct hantro_reg input_height;
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struct hantro_reg output_width;
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struct hantro_reg output_height;
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struct hantro_reg input_fmt;
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struct hantro_reg output_fmt;
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struct hantro_reg orig_width;
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struct hantro_reg display_width;
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};
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struct hantro_vp9_decoded_buffer_info {
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/* Info needed when the decoded frame serves as a reference frame. */
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unsigned short width;
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unsigned short height;
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u32 bit_depth : 4;
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};
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struct hantro_decoded_buffer {
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/* Must be the first field in this struct. */
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struct v4l2_m2m_buffer base;
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union {
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struct hantro_vp9_decoded_buffer_info vp9;
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};
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};
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/* Logging helpers */
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/**
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* DOC: hantro_debug: Module parameter to control level of debugging messages.
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*
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* Level of debugging messages can be controlled by bits of
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* module parameter called "debug". Meaning of particular
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* bits is as follows:
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*
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* bit 0 - global information: mode, size, init, release
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* bit 1 - each run start/result information
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* bit 2 - contents of small controls from userspace
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* bit 3 - contents of big controls from userspace
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* bit 4 - detail fmt, ctrl, buffer q/dq information
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* bit 5 - detail function enter/leave trace information
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* bit 6 - register write/read information
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*/
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extern int hantro_debug;
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#define vpu_debug(level, fmt, args...) \
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do { \
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if (hantro_debug & BIT(level)) \
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pr_info("%s:%d: " fmt, \
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__func__, __LINE__, ##args); \
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} while (0)
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#define vpu_err(fmt, args...) \
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pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
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/* Structure access helpers. */
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static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
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{
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return container_of(fh, struct hantro_ctx, fh);
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}
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/* Register accessors. */
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static inline void vepu_write_relaxed(struct hantro_dev *vpu,
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u32 val, u32 reg)
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{
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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writel_relaxed(val, vpu->enc_base + reg);
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}
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static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
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{
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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writel(val, vpu->enc_base + reg);
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}
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static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
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{
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u32 val = readl(vpu->enc_base + reg);
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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return val;
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}
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static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
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u32 val, u32 reg)
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{
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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writel_relaxed(val, vpu->dec_base + reg);
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}
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static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
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{
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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writel(val, vpu->dec_base + reg);
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}
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static inline void hantro_write_addr(struct hantro_dev *vpu,
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unsigned long offset,
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dma_addr_t addr)
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{
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vdpu_write(vpu, addr & 0xffffffff, offset);
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}
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static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
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{
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u32 val = readl(vpu->dec_base + reg);
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vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
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return val;
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}
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static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
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const struct hantro_reg *reg,
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u32 val)
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{
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u32 v;
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v = vdpu_read(vpu, reg->base);
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v &= ~(reg->mask << reg->shift);
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v |= ((val & reg->mask) << reg->shift);
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return v;
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}
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static inline void hantro_reg_write(struct hantro_dev *vpu,
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const struct hantro_reg *reg,
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u32 val)
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{
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vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
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}
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static inline void hantro_reg_write_s(struct hantro_dev *vpu,
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const struct hantro_reg *reg,
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u32 val)
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{
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vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
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}
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void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
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dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
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static inline struct vb2_v4l2_buffer *
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hantro_get_src_buf(struct hantro_ctx *ctx)
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{
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return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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}
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static inline struct vb2_v4l2_buffer *
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hantro_get_dst_buf(struct hantro_ctx *ctx)
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{
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return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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}
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bool hantro_needs_postproc(const struct hantro_ctx *ctx,
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const struct hantro_fmt *fmt);
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static inline dma_addr_t
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hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
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{
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if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
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return ctx->postproc.dec_q[vb->index].dma;
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return vb2_dma_contig_plane_dma_addr(vb, 0);
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}
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static inline struct hantro_decoded_buffer *
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vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
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{
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return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
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}
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void hantro_postproc_disable(struct hantro_ctx *ctx);
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void hantro_postproc_enable(struct hantro_ctx *ctx);
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void hantro_postproc_free(struct hantro_ctx *ctx);
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int hantro_postproc_alloc(struct hantro_ctx *ctx);
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int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
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struct v4l2_frmsizeenum *fsize);
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#endif /* HANTRO_H_ */
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