627 lines
18 KiB
C
627 lines
18 KiB
C
/*
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* sh73a0 clock framework support
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*
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* Copyright (C) 2010 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#define FRQCRA 0xe6150000
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#define FRQCRB 0xe6150004
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#define FRQCRD 0xe61500e4
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#define VCLKCR1 0xe6150008
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#define VCLKCR2 0xe615000C
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#define VCLKCR3 0xe615001C
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#define ZBCKCR 0xe6150010
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#define FLCKCR 0xe6150014
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#define SD0CKCR 0xe6150074
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#define SD1CKCR 0xe6150078
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#define SD2CKCR 0xe615007C
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#define FSIACKCR 0xe6150018
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#define FSIBCKCR 0xe6150090
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#define SUBCKCR 0xe6150080
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#define SPUACKCR 0xe6150084
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#define SPUVCKCR 0xe6150094
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#define MSUCKCR 0xe6150088
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#define HSICKCR 0xe615008C
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#define MFCK1CR 0xe6150098
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#define MFCK2CR 0xe615009C
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#define DSITCKCR 0xe6150060
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#define DSI0PCKCR 0xe6150064
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#define DSI1PCKCR 0xe6150068
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#define DSI0PHYCR 0xe615006C
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#define DSI1PHYCR 0xe6150070
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#define PLLECR 0xe61500d0
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#define PLL0CR 0xe61500d8
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#define PLL1CR 0xe6150028
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#define PLL2CR 0xe615002c
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#define PLL3CR 0xe61500dc
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#define SMSTPCR0 0xe6150130
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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#define SMSTPCR5 0xe6150144
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#define CKSCR 0xe61500c0
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* 26MHz default rate for the EXTAL1 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh73a0_extal1_clk = {
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.rate = 26000000,
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};
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/*
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* 48MHz default rate for the EXTAL2 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh73a0_extal2_clk = {
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.rate = 48000000,
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};
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/* A fixed divide-by-2 block */
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static unsigned long div2_recalc(struct clk *clk)
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{
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return clk->parent->rate / 2;
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}
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static struct clk_ops div2_clk_ops = {
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.recalc = div2_recalc,
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};
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static unsigned long div7_recalc(struct clk *clk)
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{
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return clk->parent->rate / 7;
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}
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static struct clk_ops div7_clk_ops = {
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.recalc = div7_recalc,
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};
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static unsigned long div13_recalc(struct clk *clk)
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{
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return clk->parent->rate / 13;
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}
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static struct clk_ops div13_clk_ops = {
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.recalc = div13_recalc,
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};
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/* Divide extal1 by two */
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static struct clk extal1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh73a0_extal1_clk,
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};
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/* Divide extal2 by two */
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static struct clk extal2_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh73a0_extal2_clk,
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};
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static struct clk_ops main_clk_ops = {
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.recalc = followparent_recalc,
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};
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/* Main clock */
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static struct clk main_clk = {
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.ops = &main_clk_ops,
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};
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/* Divide Main clock by two */
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static struct clk main_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &main_clk,
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};
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/* PLL0, PLL1, PLL2, PLL3 */
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
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mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
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/* handle CFG bit for PLL1 and PLL2 */
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switch (clk->enable_bit) {
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case 1:
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case 2:
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if (__raw_readl(clk->enable_reg) & (1 << 20))
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mult *= 2;
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}
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}
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return clk->parent->rate * mult;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll0_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &main_clk,
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.enable_reg = (void __iomem *)PLL0CR,
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.enable_bit = 0,
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};
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static struct clk pll1_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &main_clk,
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.enable_reg = (void __iomem *)PLL1CR,
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.enable_bit = 1,
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};
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static struct clk pll2_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &main_clk,
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.enable_reg = (void __iomem *)PLL2CR,
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.enable_bit = 2,
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};
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static struct clk pll3_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &main_clk,
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.enable_reg = (void __iomem *)PLL3CR,
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.enable_bit = 3,
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};
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/* Divide PLL */
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static struct clk pll1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &pll1_clk,
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};
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static struct clk pll1_div7_clk = {
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.ops = &div7_clk_ops,
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.parent = &pll1_clk,
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};
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static struct clk pll1_div13_clk = {
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.ops = &div13_clk_ops,
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.parent = &pll1_clk,
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};
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/* External input clock */
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struct clk sh73a0_extcki_clk = {
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};
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struct clk sh73a0_extalr_clk = {
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};
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static struct clk *main_clks[] = {
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&r_clk,
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&sh73a0_extal1_clk,
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&sh73a0_extal2_clk,
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&extal1_div2_clk,
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&extal2_div2_clk,
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&main_clk,
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&main_div2_clk,
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&pll0_clk,
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&pll1_clk,
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&pll2_clk,
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&pll3_clk,
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&pll1_div2_clk,
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&pll1_div7_clk,
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&pll1_div13_clk,
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&sh73a0_extcki_clk,
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&sh73a0_extalr_clk,
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};
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in FRQCRB to update hardware setting */
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value = __raw_readl(FRQCRB);
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value |= (1 << 31);
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__raw_writel(value, FRQCRB);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
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24, 0, 36, 48, 7 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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.kick = div4_kick,
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};
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enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
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DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
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[DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
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[DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
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[DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
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[DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
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[DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
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[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
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[DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
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[DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
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[DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
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};
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
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DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
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DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
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DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
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DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
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DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_NR };
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static struct clk *vck_parent[8] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &sh73a0_extcki_clk,
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[3] = &sh73a0_extal2_clk,
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[4] = &main_div2_clk,
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[5] = &sh73a0_extalr_clk,
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[6] = &main_clk,
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};
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static struct clk *pll_parent[4] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &pll1_div13_clk,
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};
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static struct clk *hsi_parent[4] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &pll1_div7_clk,
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};
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static struct clk *pll_extal2_parent[] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &sh73a0_extal2_clk,
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[3] = &sh73a0_extal2_clk,
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};
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static struct clk *dsi_parent[8] = {
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[0] = &pll1_div2_clk,
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[1] = &pll2_clk,
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[2] = &main_clk,
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[3] = &sh73a0_extal2_clk,
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[4] = &sh73a0_extcki_clk,
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};
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
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vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
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[DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
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[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
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[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
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[DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
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pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
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[DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
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hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
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[DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
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pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
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[DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
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dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
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[DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
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dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
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};
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/* DSI DIV */
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static unsigned long dsiphy_recalc(struct clk *clk)
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{
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u32 value;
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value = __raw_readl(clk->mapping->base);
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/* FIXME */
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if (!(value & 0x000B8000))
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return clk->parent->rate;
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value &= 0x3f;
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value += 1;
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if ((value < 12) ||
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(value > 33)) {
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pr_err("DSIPHY has wrong value (%d)", value);
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return 0;
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}
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return clk->parent->rate / value;
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}
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static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_mult_range_round(clk, 12, 33, rate);
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}
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static void dsiphy_disable(struct clk *clk)
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{
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u32 value;
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value = __raw_readl(clk->mapping->base);
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value &= ~0x000B8000;
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__raw_writel(value , clk->mapping->base);
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}
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static int dsiphy_enable(struct clk *clk)
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{
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u32 value;
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int multi;
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value = __raw_readl(clk->mapping->base);
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multi = (value & 0x3f) + 1;
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if ((multi < 12) || (multi > 33))
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return -EIO;
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__raw_writel(value | 0x000B8000, clk->mapping->base);
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return 0;
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}
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static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 value;
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int idx;
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idx = rate / clk->parent->rate;
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if ((idx < 12) || (idx > 33))
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return -EINVAL;
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idx += -1;
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value = __raw_readl(clk->mapping->base);
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value = (value & ~0x3f) + idx;
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__raw_writel(value, clk->mapping->base);
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return 0;
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}
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static struct clk_ops dsiphy_clk_ops = {
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.recalc = dsiphy_recalc,
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.round_rate = dsiphy_round_rate,
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.set_rate = dsiphy_set_rate,
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.enable = dsiphy_enable,
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.disable = dsiphy_disable,
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};
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static struct clk_mapping dsi0phy_clk_mapping = {
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.phys = DSI0PHYCR,
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.len = 4,
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};
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static struct clk_mapping dsi1phy_clk_mapping = {
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.phys = DSI1PHYCR,
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.len = 4,
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};
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static struct clk dsi0phy_clk = {
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.ops = &dsiphy_clk_ops,
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.parent = &div6_clks[DIV6_DSI0P], /* late install */
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.mapping = &dsi0phy_clk_mapping,
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};
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static struct clk dsi1phy_clk = {
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.ops = &dsiphy_clk_ops,
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.parent = &div6_clks[DIV6_DSI1P], /* late install */
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.mapping = &dsi1phy_clk_mapping,
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};
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static struct clk *late_main_clks[] = {
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&dsi0phy_clk,
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&dsi1phy_clk,
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};
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enum { MSTP001,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
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MSTP219,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
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MSTP314, MSTP313, MSTP312, MSTP311,
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MSTP303, MSTP302, MSTP301, MSTP300,
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MSTP411, MSTP410, MSTP403,
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MSTP_NR };
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#define MSTP(_parent, _reg, _bit, _flags) \
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SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
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[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
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[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
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[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
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[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
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[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
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[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
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[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
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[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
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[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
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[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
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[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
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[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
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[MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
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[MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
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[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
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[MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
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[MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
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[MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
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[MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
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[MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */
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[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
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[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
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[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("r_clk", &r_clk),
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/* DIV6 clocks */
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CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
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CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
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CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
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CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
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CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
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CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
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CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
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CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
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CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
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CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
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CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
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CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
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CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
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CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
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CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
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CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
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CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
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CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
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CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
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CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
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CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
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CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */
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CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
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CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
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CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
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};
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void __init sh73a0_clock_init(void)
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{
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int k, ret = 0;
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/* Set SDHI clocks to a known state */
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__raw_writel(0x108, SD0CKCR);
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__raw_writel(0x108, SD1CKCR);
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__raw_writel(0x108, SD2CKCR);
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/* detect main clock parent */
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switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
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case 0:
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main_clk.parent = &sh73a0_extal1_clk;
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break;
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case 1:
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main_clk.parent = &extal1_div2_clk;
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break;
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case 2:
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main_clk.parent = &sh73a0_extal2_clk;
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break;
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case 3:
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|
main_clk.parent = &extal2_div2_clk;
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break;
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
|
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ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
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if (!ret)
|
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
|
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ret = clk_register(late_main_clks[k]);
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|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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|
|
if (!ret)
|
|
clk_init();
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else
|
|
panic("failed to setup sh73a0 clocks\n");
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}
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