Li Peng 9553426372 drm/i915: Add CxSR support on Pineview DDR3 ... Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>		2010-05-26 14:22:51 -07:00
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drm	drm/i915: Add CxSR support on Pineview DDR3	2010-05-26 14:22:51 -07:00
vga	Merge remote branch 'anholt/drm-intel-next' into drm-next	2010-05-19 09:35:51 +10:00
Makefile	PCI/GPU: implement VGA arbitration on Linux	2009-09-09 13:29:36 -07:00