533 lines
14 KiB
C
533 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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* Inspired from: fsl-imx25-tsadc
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*
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "stm32-adc-core.h"
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/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
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#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
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/* STM32F4_ADC_CSR - bit fields */
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#define STM32F4_EOC3 BIT(17)
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#define STM32F4_EOC2 BIT(9)
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#define STM32F4_EOC1 BIT(1)
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/* STM32F4_ADC_CCR - bit fields */
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#define STM32F4_ADC_ADCPRE_SHIFT 16
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#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
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/* STM32 F4 maximum analog clock rate (from datasheet) */
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#define STM32F4_ADC_MAX_CLK_RATE 36000000
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/* STM32H7 - common registers for all ADC instances */
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#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
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#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
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/* STM32H7_ADC_CSR - bit fields */
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#define STM32H7_EOC_SLV BIT(18)
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#define STM32H7_EOC_MST BIT(2)
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/* STM32H7_ADC_CCR - bit fields */
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#define STM32H7_PRESC_SHIFT 18
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#define STM32H7_PRESC_MASK GENMASK(21, 18)
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#define STM32H7_CKMODE_SHIFT 16
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#define STM32H7_CKMODE_MASK GENMASK(17, 16)
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/* STM32 H7 maximum analog clock rate (from datasheet) */
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#define STM32H7_ADC_MAX_CLK_RATE 36000000
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/**
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* stm32_adc_common_regs - stm32 common registers, compatible dependent data
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* @csr: common status register offset
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* @eoc1: adc1 end of conversion flag in @csr
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* @eoc2: adc2 end of conversion flag in @csr
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* @eoc3: adc3 end of conversion flag in @csr
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*/
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struct stm32_adc_common_regs {
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u32 csr;
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u32 eoc1_msk;
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u32 eoc2_msk;
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u32 eoc3_msk;
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};
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struct stm32_adc_priv;
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/**
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* stm32_adc_priv_cfg - stm32 core compatible configuration data
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* @regs: common registers for all instances
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* @clk_sel: clock selection routine
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*/
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struct stm32_adc_priv_cfg {
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const struct stm32_adc_common_regs *regs;
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int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
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};
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/**
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* struct stm32_adc_priv - stm32 ADC core private data
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* @irq: irq for ADC block
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* @domain: irq domain reference
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* @aclk: clock reference for the analog circuitry
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* @bclk: bus clock common for all ADCs, depends on part used
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* @vref: regulator reference
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* @cfg: compatible configuration data
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* @common: common data for all ADC instances
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*/
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struct stm32_adc_priv {
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int irq;
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struct irq_domain *domain;
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struct clk *aclk;
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struct clk *bclk;
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struct regulator *vref;
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const struct stm32_adc_priv_cfg *cfg;
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struct stm32_adc_common common;
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};
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static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
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{
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return container_of(com, struct stm32_adc_priv, common);
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}
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/* STM32F4 ADC internal common clock prescaler division ratios */
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static int stm32f4_pclk_div[] = {2, 4, 6, 8};
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/**
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* stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
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* @priv: stm32 ADC core private data
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* Select clock prescaler used for analog conversions, before using ADC.
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*/
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static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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unsigned long rate;
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u32 val;
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int i;
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/* stm32f4 has one clk input for analog (mandatory), enforce it here */
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if (!priv->aclk) {
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dev_err(&pdev->dev, "No 'adc' clock found\n");
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return -ENOENT;
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}
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rate = clk_get_rate(priv->aclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid clock rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
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if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
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break;
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}
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if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
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dev_err(&pdev->dev, "adc clk selection failed\n");
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return -EINVAL;
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}
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priv->common.rate = rate / stm32f4_pclk_div[i];
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val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
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val &= ~STM32F4_ADC_ADCPRE_MASK;
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val |= i << STM32F4_ADC_ADCPRE_SHIFT;
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writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
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dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
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priv->common.rate / 1000);
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return 0;
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}
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/**
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* struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
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* @ckmode: ADC clock mode, Async or sync with prescaler.
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* @presc: prescaler bitfield for async clock mode
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* @div: prescaler division ratio
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*/
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struct stm32h7_adc_ck_spec {
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u32 ckmode;
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u32 presc;
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int div;
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};
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static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
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/* 00: CK_ADC[1..3]: Asynchronous clock modes */
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{ 0, 0, 1 },
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{ 0, 1, 2 },
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{ 0, 2, 4 },
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{ 0, 3, 6 },
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{ 0, 4, 8 },
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{ 0, 5, 10 },
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{ 0, 6, 12 },
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{ 0, 7, 16 },
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{ 0, 8, 32 },
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{ 0, 9, 64 },
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{ 0, 10, 128 },
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{ 0, 11, 256 },
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/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
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{ 1, 0, 1 },
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{ 2, 0, 2 },
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{ 3, 0, 4 },
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};
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static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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u32 ckmode, presc, val;
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unsigned long rate;
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int i, div;
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/* stm32h7 bus clock is common for all ADC instances (mandatory) */
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if (!priv->bclk) {
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dev_err(&pdev->dev, "No 'bus' clock found\n");
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return -ENOENT;
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}
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/*
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* stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
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* So, choice is to have bus clock mandatory and adc clock optional.
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* If optional 'adc' clock has been found, then try to use it first.
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*/
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if (priv->aclk) {
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/*
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* Asynchronous clock modes (e.g. ckmode == 0)
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* From spec: PLL output musn't exceed max rate
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*/
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rate = clk_get_rate(priv->aclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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}
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/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
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rate = clk_get_rate(priv->bclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (!ckmode)
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continue;
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if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
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goto out;
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}
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dev_err(&pdev->dev, "adc clk selection failed\n");
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return -EINVAL;
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out:
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/* rate used later by each ADC instance to control BOOST mode */
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priv->common.rate = rate / div;
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/* Set common clock mode and prescaler */
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val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
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val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
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val |= ckmode << STM32H7_CKMODE_SHIFT;
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val |= presc << STM32H7_PRESC_SHIFT;
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writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
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dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
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ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
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return 0;
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}
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/* STM32F4 common registers definitions */
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static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.csr = STM32F4_ADC_CSR,
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.eoc1_msk = STM32F4_EOC1,
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.eoc2_msk = STM32F4_EOC2,
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.eoc3_msk = STM32F4_EOC3,
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};
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/* STM32H7 common registers definitions */
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static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
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.csr = STM32H7_ADC_CSR,
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.eoc1_msk = STM32H7_EOC_MST,
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.eoc2_msk = STM32H7_EOC_SLV,
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};
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/* ADC common interrupt for all instances */
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static void stm32_adc_irq_handler(struct irq_desc *desc)
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{
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struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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chained_irq_enter(chip, desc);
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status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
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if (status & priv->cfg->regs->eoc1_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 0));
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if (status & priv->cfg->regs->eoc2_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 1));
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if (status & priv->cfg->regs->eoc3_msk)
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generic_handle_irq(irq_find_mapping(priv->domain, 2));
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chained_irq_exit(chip, desc);
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};
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static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, d->host_data);
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
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return 0;
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}
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static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops stm32_adc_domain_ops = {
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.map = stm32_adc_domain_map,
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.unmap = stm32_adc_domain_unmap,
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.xlate = irq_domain_xlate_onecell,
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};
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static int stm32_adc_irq_probe(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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struct device_node *np = pdev->dev.of_node;
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priv->irq = platform_get_irq(pdev, 0);
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if (priv->irq < 0) {
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dev_err(&pdev->dev, "failed to get irq\n");
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return priv->irq;
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}
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priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
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&stm32_adc_domain_ops,
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priv);
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if (!priv->domain) {
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dev_err(&pdev->dev, "Failed to add irq domain\n");
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return -ENOMEM;
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}
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irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
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irq_set_handler_data(priv->irq, priv);
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return 0;
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}
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static void stm32_adc_irq_remove(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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int hwirq;
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for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
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irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
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irq_domain_remove(priv->domain);
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irq_set_chained_handler(priv->irq, NULL);
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}
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static int stm32_adc_probe(struct platform_device *pdev)
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{
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struct stm32_adc_priv *priv;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct resource *res;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->cfg = (const struct stm32_adc_priv_cfg *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->common.base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->common.base))
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return PTR_ERR(priv->common.base);
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priv->common.phys_base = res->start;
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priv->vref = devm_regulator_get(&pdev->dev, "vref");
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if (IS_ERR(priv->vref)) {
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ret = PTR_ERR(priv->vref);
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dev_err(&pdev->dev, "vref get failed, %d\n", ret);
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return ret;
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}
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ret = regulator_enable(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref enable failed\n");
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return ret;
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}
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ret = regulator_get_voltage(priv->vref);
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if (ret < 0) {
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dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
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goto err_regulator_disable;
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}
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priv->common.vref_mv = ret / 1000;
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dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
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priv->aclk = devm_clk_get(&pdev->dev, "adc");
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if (IS_ERR(priv->aclk)) {
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ret = PTR_ERR(priv->aclk);
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if (ret == -ENOENT) {
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priv->aclk = NULL;
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} else {
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dev_err(&pdev->dev, "Can't get 'adc' clock\n");
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goto err_regulator_disable;
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}
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}
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if (priv->aclk) {
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ret = clk_prepare_enable(priv->aclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_regulator_disable;
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}
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}
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priv->bclk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(priv->bclk)) {
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ret = PTR_ERR(priv->bclk);
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if (ret == -ENOENT) {
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priv->bclk = NULL;
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} else {
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dev_err(&pdev->dev, "Can't get 'bus' clock\n");
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goto err_aclk_disable;
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}
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}
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if (priv->bclk) {
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ret = clk_prepare_enable(priv->bclk);
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if (ret < 0) {
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dev_err(&pdev->dev, "adc clk enable failed\n");
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goto err_aclk_disable;
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}
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}
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ret = priv->cfg->clk_sel(pdev, priv);
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if (ret < 0)
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goto err_bclk_disable;
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ret = stm32_adc_irq_probe(pdev, priv);
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if (ret < 0)
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goto err_bclk_disable;
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platform_set_drvdata(pdev, &priv->common);
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ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to populate DT children\n");
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goto err_irq_remove;
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}
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return 0;
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err_irq_remove:
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stm32_adc_irq_remove(pdev, priv);
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err_bclk_disable:
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if (priv->bclk)
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clk_disable_unprepare(priv->bclk);
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err_aclk_disable:
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if (priv->aclk)
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clk_disable_unprepare(priv->aclk);
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err_regulator_disable:
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regulator_disable(priv->vref);
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return ret;
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}
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static int stm32_adc_remove(struct platform_device *pdev)
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{
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struct stm32_adc_common *common = platform_get_drvdata(pdev);
|
|
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
|
|
|
|
of_platform_depopulate(&pdev->dev);
|
|
stm32_adc_irq_remove(pdev, priv);
|
|
if (priv->bclk)
|
|
clk_disable_unprepare(priv->bclk);
|
|
if (priv->aclk)
|
|
clk_disable_unprepare(priv->aclk);
|
|
regulator_disable(priv->vref);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
|
|
.regs = &stm32f4_adc_common_regs,
|
|
.clk_sel = stm32f4_adc_clk_sel,
|
|
};
|
|
|
|
static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
|
|
.regs = &stm32h7_adc_common_regs,
|
|
.clk_sel = stm32h7_adc_clk_sel,
|
|
};
|
|
|
|
static const struct of_device_id stm32_adc_of_match[] = {
|
|
{
|
|
.compatible = "st,stm32f4-adc-core",
|
|
.data = (void *)&stm32f4_adc_priv_cfg
|
|
}, {
|
|
.compatible = "st,stm32h7-adc-core",
|
|
.data = (void *)&stm32h7_adc_priv_cfg
|
|
}, {
|
|
},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
|
|
|
|
static struct platform_driver stm32_adc_driver = {
|
|
.probe = stm32_adc_probe,
|
|
.remove = stm32_adc_remove,
|
|
.driver = {
|
|
.name = "stm32-adc-core",
|
|
.of_match_table = stm32_adc_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_adc_driver);
|
|
|
|
MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:stm32-adc-core");
|