261 lines
8.5 KiB
C
261 lines
8.5 KiB
C
/*
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* file: include/asm-blackfin/mach-bf518/irq.h
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* based on: include/asm-blackfin/mach-bf527/irq.h
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* author: Michael Hennerich (michael.hennerich@analog.com)
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*
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* created:
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* description:
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* system mmr register map
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _BF518_IRQ_H_
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#define _BF518_IRQ_H_
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/*
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* Interrupt source definitions
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Event Source Core Event Name
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Core Emulation **
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Events (highest priority) EMU 0
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Reset RST 1
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NMI NMI 2
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Exception EVX 3
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Reserved -- 4
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Hardware Error IVHW 5
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Core Timer IVTMR 6 *
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.....
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Software Interrupt 1 IVG14 31
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Software Interrupt 2 --
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(lowest priority) IVG15 32 *
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*/
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#define NR_PERI_INTS (2 * 32)
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /* Emulation */
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#define IRQ_RST 1 /* reset */
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#define IRQ_NMI 2 /* Non Maskable */
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#define IRQ_EVX 3 /* Exception */
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#define IRQ_UNUSED 4 /* - unused interrupt */
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#define IRQ_HWERR 5 /* Hardware Error */
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#define IRQ_CORETMR 6 /* Core timer */
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#define BFIN_IRQ(x) ((x) + 7)
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#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
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#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
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#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
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#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
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#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
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#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
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#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
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#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
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#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
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#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
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#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
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#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
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#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
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#define IRQ_RTC BFIN_IRQ(14) /* RTC */
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#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
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#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
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#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
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#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
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#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
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#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
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#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
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#define IRQ_TWI BFIN_IRQ(20) /* TWI */
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#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
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#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
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#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
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#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
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#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
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#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
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#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
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#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
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#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
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#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
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#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
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#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
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#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
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#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
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#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
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#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
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#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
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#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
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#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
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#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
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#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
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#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
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#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
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#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
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#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
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#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
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#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
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#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
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#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
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#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
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#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
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#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
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#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
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#define SYS_IRQS BFIN_IRQ(63) /* 70 */
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#define IRQ_PF0 71
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#define IRQ_PF1 72
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#define IRQ_PF2 73
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#define IRQ_PF3 74
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#define IRQ_PF4 75
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#define IRQ_PF5 76
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#define IRQ_PF6 77
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#define IRQ_PF7 78
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#define IRQ_PF8 79
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#define IRQ_PF9 80
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#define IRQ_PF10 81
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#define IRQ_PF11 82
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#define IRQ_PF12 83
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#define IRQ_PF13 84
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#define IRQ_PF14 85
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#define IRQ_PF15 86
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#define IRQ_PG0 87
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#define IRQ_PG1 88
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#define IRQ_PG2 89
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#define IRQ_PG3 90
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#define IRQ_PG4 91
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#define IRQ_PG5 92
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#define IRQ_PG6 93
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#define IRQ_PG7 94
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#define IRQ_PG8 95
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#define IRQ_PG9 96
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#define IRQ_PG10 97
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#define IRQ_PG11 98
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#define IRQ_PG12 99
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#define IRQ_PG13 100
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#define IRQ_PG14 101
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#define IRQ_PG15 102
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#define IRQ_PH0 103
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#define IRQ_PH1 104
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#define IRQ_PH2 105
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#define IRQ_PH3 106
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#define IRQ_PH4 107
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#define IRQ_PH5 108
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#define IRQ_PH6 109
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#define IRQ_PH7 110
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#define IRQ_PH8 111
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#define IRQ_PH9 112
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#define IRQ_PH10 113
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#define IRQ_PH11 114
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#define IRQ_PH12 115
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#define IRQ_PH13 116
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#define IRQ_PH14 117
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#define IRQ_PH15 118
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#define GPIO_IRQ_BASE IRQ_PF0
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#define NR_IRQS (IRQ_PH15 + 1)
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#define IVG7 7
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#define IVG8 8
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#define IVG9 9
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#define IVG10 10
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#define IVG11 11
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#define IVG12 12
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#define IVG13 13
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#define IVG14 14
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#define IVG15 15
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/* IAR0 BIT FIELDS */
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA0_ERROR_POS 4
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#define IRQ_DMAR0_BLK_POS 8
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#define IRQ_DMAR1_BLK_POS 12
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#define IRQ_DMAR0_OVR_POS 16
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#define IRQ_DMAR1_OVR_POS 20
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#define IRQ_PPI_ERROR_POS 24
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#define IRQ_MAC_ERROR_POS 28
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/* IAR1 BIT FIELDS */
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#define IRQ_SPORT0_ERROR_POS 0
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#define IRQ_SPORT1_ERROR_POS 4
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#define IRQ_PTP_ERROR_POS 8
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#define IRQ_UART0_ERROR_POS 16
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#define IRQ_UART1_ERROR_POS 20
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#define IRQ_RTC_POS 24
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#define IRQ_PPI_POS 28
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/* IAR2 BIT FIELDS */
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#define IRQ_SPORT0_RX_POS 0
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#define IRQ_SPORT0_TX_POS 4
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#define IRQ_RSI_POS 4
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#define IRQ_SPORT1_RX_POS 8
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#define IRQ_SPI1_POS 8
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#define IRQ_SPORT1_TX_POS 12
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#define IRQ_TWI_POS 16
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#define IRQ_SPI0_POS 20
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#define IRQ_UART0_RX_POS 24
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#define IRQ_UART0_TX_POS 28
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/* IAR3 BIT FIELDS */
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#define IRQ_UART1_RX_POS 0
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#define IRQ_UART1_TX_POS 4
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#define IRQ_OPTSEC_POS 8
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#define IRQ_CNT_POS 12
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#define IRQ_MAC_RX_POS 16
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#define IRQ_PORTH_INTA_POS 20
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#define IRQ_MAC_TX_POS 24
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#define IRQ_PORTH_INTB_POS 28
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/* IAR4 BIT FIELDS */
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#define IRQ_TIMER0_POS 0
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#define IRQ_TIMER1_POS 4
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#define IRQ_TIMER2_POS 8
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#define IRQ_TIMER3_POS 12
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#define IRQ_TIMER4_POS 16
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#define IRQ_TIMER5_POS 20
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#define IRQ_TIMER6_POS 24
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#define IRQ_TIMER7_POS 28
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/* IAR5 BIT FIELDS */
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#define IRQ_PORTG_INTA_POS 0
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#define IRQ_PORTG_INTB_POS 4
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#define IRQ_MEM_DMA0_POS 8
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#define IRQ_MEM_DMA1_POS 12
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#define IRQ_WATCH_POS 16
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#define IRQ_PORTF_INTA_POS 20
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#define IRQ_PORTF_INTB_POS 24
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#define IRQ_SPI0_ERROR_POS 28
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/* IAR6 BIT FIELDS */
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#define IRQ_SPI1_ERROR_POS 0
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#define IRQ_RSI_INT0_POS 12
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#define IRQ_RSI_INT1_POS 16
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#define IRQ_PWM_TRIP_POS 20
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#define IRQ_PWM_SYNC_POS 24
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#define IRQ_PTP_STAT_POS 28
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#endif /* _BF518_IRQ_H_ */
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