307 lines
8.3 KiB
Plaintext
307 lines
8.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2017-2020 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*
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*/
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#include "mt7623.dtsi"
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#include <dt-bindings/memory/mt2701-larb-port.h>
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/ {
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aliases {
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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};
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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"syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <0>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <1>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <2>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt7623-m4u",
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"mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt7623-jpgdec",
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"mediatek,mt2701-jpgdec";
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reg = <0 0x15004000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt7623-smi-common",
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"mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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ovl: ovl@14007000 {
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compatible = "mediatek,mt7623-disp-ovl",
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"mediatek,mt2701-disp-ovl";
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reg = <0 0x14007000 0 0x1000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_OVL>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
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mediatek,larb = <&larb0>;
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};
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rdma0: rdma@14008000 {
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compatible = "mediatek,mt7623-disp-rdma",
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"mediatek,mt2701-disp-rdma";
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reg = <0 0x14008000 0 0x1000>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_RDMA>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
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mediatek,larb = <&larb0>;
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};
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wdma@14009000 {
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compatible = "mediatek,mt7623-disp-wdma",
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"mediatek,mt2701-disp-wdma";
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reg = <0 0x14009000 0 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_WDMA>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
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mediatek,larb = <&larb0>;
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};
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bls: pwm@1400a000 {
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compatible = "mediatek,mt7623-disp-pwm",
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"mediatek,mt2701-disp-pwm";
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reg = <0 0x1400a000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
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<&mmsys CLK_MM_DISP_BLS>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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color: color@1400b000 {
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compatible = "mediatek,mt7623-disp-color",
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"mediatek,mt2701-disp-color";
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reg = <0 0x1400b000 0 0x1000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_COLOR>;
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};
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dsi: dsi@1400c000 {
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compatible = "mediatek,mt7623-dsi",
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"mediatek,mt2701-dsi";
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reg = <0 0x1400c000 0 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DSI_ENGINE>,
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<&mmsys CLK_MM_DSI_DIG>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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status = "disabled";
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};
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mutex: mutex@1400e000 {
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compatible = "mediatek,mt7623-disp-mutex",
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"mediatek,mt2701-disp-mutex";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_MUTEX_32K>;
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};
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rdma1: rdma@14012000 {
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compatible = "mediatek,mt7623-disp-rdma",
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"mediatek,mt2701-disp-rdma";
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reg = <0 0x14012000 0 0x1000>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DISP_RDMA1>;
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iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
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mediatek,larb = <&larb0>;
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};
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dpi0: dpi@14014000 {
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compatible = "mediatek,mt7623-dpi",
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"mediatek,mt2701-dpi";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_DPI1_DIGL>,
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<&mmsys CLK_MM_DPI1_ENGINE>,
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<&apmixedsys CLK_APMIXED_TVDPLL>;
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clock-names = "pixel", "engine", "pll";
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status = "disabled";
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};
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hdmi0: hdmi@14015000 {
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compatible = "mediatek,mt7623-hdmi",
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"mediatek,mt2701-hdmi";
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reg = <0 0x14015000 0 0x400>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLL>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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cec = <&cec>;
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status = "disabled";
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};
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mipi_tx0: dsi-phy@10010000 {
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compatible = "mediatek,mt7623-mipi-tx",
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"mediatek,mt2701-mipi-tx";
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reg = <0 0x10010000 0 0x90>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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cec: cec@10012000 {
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compatible = "mediatek,mt7623-cec",
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"mediatek,mt8173-cec";
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reg = <0 0x10012000 0 0xbc>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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status = "disabled";
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};
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hdmi_phy: hdmi-phy@10209100 {
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compatible = "mediatek,mt7623-hdmi-phy",
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"mediatek,mt2701-hdmi-phy";
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reg = <0 0x10209100 0 0x24>;
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clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
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clock-names = "pll_ref";
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clock-output-names = "hdmitx_dig_cts";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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hdmiddc0: i2c@11013000 {
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compatible = "mediatek,mt7623-hdmi-ddc",
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"mediatek,mt8173-hdmi-ddc";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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reg = <0 0x11013000 0 0x1C>;
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clocks = <&pericfg CLK_PERI_I2C3>;
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clock-names = "ddc-i2c";
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status = "disabled";
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};
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};
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&pio {
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hdmi_pins_a: hdmi-default {
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pins-hdmi {
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pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
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input-enable;
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bias-pull-down;
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};
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};
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hdmi_ddc_pins_a: hdmi_ddc-default {
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pins-hdmi-ddc {
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pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
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<MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
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};
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};
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};
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