417 lines
12 KiB
C
417 lines
12 KiB
C
/******************************************************************************
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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#include "iwl-agn-hw.h"
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#include "iwl-agn.h"
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static const s8 iwlagn_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWLAGN_CMD_FIFO_NUM,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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};
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/*
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* ucode
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*/
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static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
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struct fw_desc *image, u32 dst_addr)
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{
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dma_addr_t phy_addr = image->p_addr;
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u32 byte_cnt = image->len;
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int ret;
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priv->ucode_write_complete = 0;
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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iwl_write_direct32(priv,
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FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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iwl_write_direct32(priv,
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FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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iwl_write_direct32(priv,
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FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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(iwl_get_dma_hi_addr(phy_addr)
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<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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iwl_write_direct32(priv,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
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ret = wait_event_interruptible_timeout(priv->wait_command_queue,
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priv->ucode_write_complete, 5 * HZ);
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if (ret == -ERESTARTSYS) {
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IWL_ERR(priv, "Could not load the %s uCode section due "
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"to interrupt\n", name);
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return ret;
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}
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if (!ret) {
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IWL_ERR(priv, "Could not load the %s uCode section\n",
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name);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int iwlagn_load_given_ucode(struct iwl_priv *priv,
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struct fw_desc *inst_image,
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struct fw_desc *data_image)
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{
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int ret = 0;
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ret = iwlagn_load_section(priv, "INST", inst_image,
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IWLAGN_RTC_INST_LOWER_BOUND);
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if (ret)
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return ret;
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return iwlagn_load_section(priv, "DATA", data_image,
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IWLAGN_RTC_DATA_LOWER_BOUND);
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}
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int iwlagn_load_ucode(struct iwl_priv *priv)
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{
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int ret = 0;
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/* check whether init ucode should be loaded, or rather runtime ucode */
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if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
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IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
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ret = iwlagn_load_given_ucode(priv,
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&priv->ucode_init, &priv->ucode_init_data);
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if (!ret) {
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IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
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priv->ucode_type = UCODE_INIT;
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}
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} else {
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IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
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"Loading runtime ucode...\n");
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ret = iwlagn_load_given_ucode(priv,
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&priv->ucode_code, &priv->ucode_data);
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if (!ret) {
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IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
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priv->ucode_type = UCODE_RT;
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}
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}
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return ret;
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}
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#define IWL_UCODE_GET(item) \
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static u32 iwlagn_ucode_get_##item(const struct iwl_ucode_header *ucode,\
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u32 api_ver) \
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{ \
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if (api_ver <= 2) \
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return le32_to_cpu(ucode->u.v1.item); \
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return le32_to_cpu(ucode->u.v2.item); \
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}
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static u32 iwlagn_ucode_get_header_size(u32 api_ver)
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{
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if (api_ver <= 2)
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return UCODE_HEADER_SIZE(1);
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return UCODE_HEADER_SIZE(2);
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}
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static u32 iwlagn_ucode_get_build(const struct iwl_ucode_header *ucode,
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u32 api_ver)
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{
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if (api_ver <= 2)
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return 0;
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return le32_to_cpu(ucode->u.v2.build);
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}
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static u8 *iwlagn_ucode_get_data(const struct iwl_ucode_header *ucode,
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u32 api_ver)
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{
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if (api_ver <= 2)
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return (u8 *) ucode->u.v1.data;
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return (u8 *) ucode->u.v2.data;
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}
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IWL_UCODE_GET(inst_size);
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IWL_UCODE_GET(data_size);
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IWL_UCODE_GET(init_size);
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IWL_UCODE_GET(init_data_size);
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IWL_UCODE_GET(boot_size);
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struct iwl_ucode_ops iwlagn_ucode = {
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.get_header_size = iwlagn_ucode_get_header_size,
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.get_build = iwlagn_ucode_get_build,
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.get_inst_size = iwlagn_ucode_get_inst_size,
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.get_data_size = iwlagn_ucode_get_data_size,
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.get_init_size = iwlagn_ucode_get_init_size,
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.get_init_data_size = iwlagn_ucode_get_init_data_size,
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.get_boot_size = iwlagn_ucode_get_boot_size,
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.get_data = iwlagn_ucode_get_data,
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};
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/*
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* Calibration
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*/
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static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
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{
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struct iwl_calib_xtal_freq_cmd cmd;
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__le16 *xtal_calib =
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(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
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cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
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return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
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(u8 *)&cmd, sizeof(cmd));
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}
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static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
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{
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struct iwl_calib_cfg_cmd calib_cfg_cmd;
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struct iwl_host_cmd cmd = {
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.id = CALIBRATION_CFG_CMD,
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.len = sizeof(struct iwl_calib_cfg_cmd),
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.data = &calib_cfg_cmd,
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};
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memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
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calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
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return iwl_send_cmd(priv, &cmd);
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}
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void iwlagn_rx_calib_result(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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{
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struct iwl_rx_packet *pkt = rxb_addr(rxb);
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struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
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int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
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int index;
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/* reduce the size of the length field itself */
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len -= 4;
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/* Define the order in which the results will be sent to the runtime
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* uCode. iwl_send_calib_results sends them in a row according to
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* their index. We sort them here
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*/
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switch (hdr->op_code) {
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case IWL_PHY_CALIBRATE_DC_CMD:
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index = IWL_CALIB_DC;
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break;
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case IWL_PHY_CALIBRATE_LO_CMD:
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index = IWL_CALIB_LO;
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break;
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case IWL_PHY_CALIBRATE_TX_IQ_CMD:
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index = IWL_CALIB_TX_IQ;
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break;
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case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
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index = IWL_CALIB_TX_IQ_PERD;
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break;
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case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
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index = IWL_CALIB_BASE_BAND;
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break;
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default:
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IWL_ERR(priv, "Unknown calibration notification %d\n",
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hdr->op_code);
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return;
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}
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iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
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}
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void iwlagn_rx_calib_complete(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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{
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IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
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queue_work(priv->workqueue, &priv->restart);
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}
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void iwlagn_init_alive_start(struct iwl_priv *priv)
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{
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int ret = 0;
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/* Check alive response for "valid" sign from uCode */
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if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
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/* We had an error bringing up the hardware, so take it
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* all the way back down so we can try again */
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IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
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goto restart;
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}
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/* initialize uCode was loaded... verify inst image.
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* This is a paranoid check, because we would not have gotten the
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* "initialize" alive if code weren't properly loaded. */
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if (iwl_verify_ucode(priv)) {
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/* Runtime instruction load was bad;
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* take it all the way back down so we can try again */
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IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
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goto restart;
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}
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ret = priv->cfg->ops->lib->alive_notify(priv);
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if (ret) {
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IWL_WARN(priv,
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"Could not complete ALIVE transition: %d\n", ret);
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goto restart;
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}
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iwlagn_send_calib_cfg(priv);
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return;
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restart:
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/* real restart (first load init_ucode) */
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queue_work(priv->workqueue, &priv->restart);
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}
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int iwlagn_alive_notify(struct iwl_priv *priv)
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{
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u32 a;
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unsigned long flags;
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int i, chan;
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u32 reg_val;
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spin_lock_irqsave(&priv->lock, flags);
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priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
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for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr +
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IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
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iwl_write_targ_mem(priv, a, 0);
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iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
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priv->scd_bc_tbls.dma >> 10);
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/* Enable DMA channel */
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for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Update FH chicken bits */
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reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
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iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
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IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
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/* initiate the queues */
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for (i = 0; i < priv->hw_params.max_txq_num; i++) {
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iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
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sizeof(u32),
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((SCD_WIN_SIZE <<
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IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((SCD_FRAME_LIMIT <<
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IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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}
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iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
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IWL_MASK(0, priv->hw_params.max_txq_num));
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* make sure all queue are not stopped */
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memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
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for (i = 0; i < 4; i++)
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atomic_set(&priv->queue_stop_count[i], 0);
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/* reset to 0 to enable all the queue first */
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priv->txq_ctx_active_msk = 0;
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/* map qos queues to fifos one-to-one */
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BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
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for (i = 0; i < ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo); i++) {
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int ac = iwlagn_default_queue_to_tx_fifo[i];
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iwl_txq_ctx_activate(priv, i);
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if (ac == IWL_TX_FIFO_UNUSED)
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continue;
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iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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iwl_send_wimax_coex(priv);
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iwlagn_set_Xtal_calib(priv);
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iwl_send_calib_results(priv);
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return 0;
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}
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