722202e10b
Recent SoC such as Armada 370/XP came with the possibility to deal with the I/O coherency by hardware. In this case the transaction attribute of the window must be flagged as "Shared transaction". Once this flag is set, then the transactions will be forced to be sent through the coherency block, in other case transaction is driven directly to DRAM. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Yehuda Yitschak <yehuday@marvell.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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| .. | ||
| addr-map.h | ||
| cache-feroceon-l2.h | ||
| common.h | ||
| irq.h | ||
| mpp.h | ||
| orion-gpio.h | ||
| pcie.h | ||
| time.h | ||