407 lines
11 KiB
C
407 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Christoph Hellwig.
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*
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* DMA operations that map physical memory directly without using an IOMMU.
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*/
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#include <linux/memblock.h> /* for max_pfn */
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-direct.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-contiguous.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/pfn.h>
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#include <linux/set_memory.h>
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#include <linux/swiotlb.h>
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/*
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* Most architectures use ZONE_DMA for the first 16 Megabytes, but
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* some use it for entirely different regions:
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*/
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#ifndef ARCH_ZONE_DMA_BITS
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#define ARCH_ZONE_DMA_BITS 24
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#endif
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/*
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* For AMD SEV all DMA must be to unencrypted addresses.
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*/
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static inline bool force_dma_unencrypted(void)
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{
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return sev_active();
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}
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static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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if (!dev->dma_mask) {
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dev_err_once(dev, "DMA map on device without dma_mask\n");
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} else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
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dev_err_once(dev,
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"overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
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&dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
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}
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WARN_ON_ONCE(1);
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}
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static inline dma_addr_t phys_to_dma_direct(struct device *dev,
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phys_addr_t phys)
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{
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if (force_dma_unencrypted())
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return __phys_to_dma(dev, phys);
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return phys_to_dma(dev, phys);
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}
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u64 dma_direct_get_required_mask(struct device *dev)
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{
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u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT);
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if (dev->bus_dma_mask && dev->bus_dma_mask < max_dma)
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max_dma = dev->bus_dma_mask;
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return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
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}
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static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
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u64 *phys_mask)
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{
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if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
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dma_mask = dev->bus_dma_mask;
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if (force_dma_unencrypted())
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*phys_mask = __dma_to_phys(dev, dma_mask);
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else
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*phys_mask = dma_to_phys(dev, dma_mask);
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/*
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* Optimistically try the zone that the physical address mask falls
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* into first. If that returns memory that isn't actually addressable
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* we will fallback to the next lower zone and try again.
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*
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* Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
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* zones.
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*/
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if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
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return GFP_DMA;
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if (*phys_mask <= DMA_BIT_MASK(32))
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return GFP_DMA32;
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return 0;
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}
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static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
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{
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return phys_to_dma_direct(dev, phys) + size - 1 <=
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min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
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}
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struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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int page_order = get_order(size);
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struct page *page = NULL;
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u64 phys_mask;
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if (attrs & DMA_ATTR_NO_WARN)
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gfp |= __GFP_NOWARN;
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/* we always manually zero the memory once we are done: */
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gfp &= ~__GFP_ZERO;
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gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
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&phys_mask);
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again:
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/* CMA can be used only in the context which permits sleeping */
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if (gfpflags_allow_blocking(gfp)) {
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page = dma_alloc_from_contiguous(dev, count, page_order,
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gfp & __GFP_NOWARN);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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dma_release_from_contiguous(dev, page, count);
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page = NULL;
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}
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}
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if (!page)
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page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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__free_pages(page, page_order);
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page = NULL;
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if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
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phys_mask < DMA_BIT_MASK(64) &&
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!(gfp & (GFP_DMA32 | GFP_DMA))) {
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gfp |= GFP_DMA32;
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goto again;
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}
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if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
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gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
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goto again;
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}
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}
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return page;
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}
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void *dma_direct_alloc_pages(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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struct page *page;
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void *ret;
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page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
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if (!page)
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return NULL;
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if (PageHighMem(page)) {
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/*
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* Depending on the cma= arguments and per-arch setup
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* dma_alloc_from_contiguous could return highmem pages.
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* Without remapping there is no way to return them here,
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* so log an error and fail.
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*/
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dev_info(dev, "Rejecting highmem page from CMA.\n");
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__dma_direct_free_pages(dev, size, page);
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return NULL;
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}
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ret = page_address(page);
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if (force_dma_unencrypted()) {
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set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
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*dma_handle = __phys_to_dma(dev, page_to_phys(page));
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} else {
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*dma_handle = phys_to_dma(dev, page_to_phys(page));
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}
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memset(ret, 0, size);
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return ret;
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}
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void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page)
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{
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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if (!dma_release_from_contiguous(dev, page, count))
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__free_pages(page, get_order(size));
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}
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void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs)
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{
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unsigned int page_order = get_order(size);
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if (force_dma_unencrypted())
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set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
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__dma_direct_free_pages(dev, size, virt_to_page(cpu_addr));
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}
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void *dma_direct_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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if (!dev_is_dma_coherent(dev))
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return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
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return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
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}
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void dma_direct_free(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
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{
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if (!dev_is_dma_coherent(dev))
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arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
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else
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dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
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}
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
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defined(CONFIG_SWIOTLB)
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void dma_direct_sync_single_for_device(struct device *dev,
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dma_addr_t addr, size_t size, enum dma_data_direction dir)
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{
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phys_addr_t paddr = dma_to_phys(dev, addr);
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_device(dev, paddr, size, dir);
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}
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EXPORT_SYMBOL(dma_direct_sync_single_for_device);
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void dma_direct_sync_sg_for_device(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
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swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length,
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dir, SYNC_FOR_DEVICE);
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_device(dev, sg_phys(sg), sg->length,
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dir);
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}
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}
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EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
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#endif
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
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defined(CONFIG_SWIOTLB)
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void dma_direct_sync_single_for_cpu(struct device *dev,
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dma_addr_t addr, size_t size, enum dma_data_direction dir)
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{
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phys_addr_t paddr = dma_to_phys(dev, addr);
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if (!dev_is_dma_coherent(dev)) {
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arch_sync_dma_for_cpu(dev, paddr, size, dir);
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arch_sync_dma_for_cpu_all(dev);
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}
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
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}
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EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
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void dma_direct_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
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if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
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swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length, dir,
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SYNC_FOR_CPU);
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}
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if (!dev_is_dma_coherent(dev))
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arch_sync_dma_for_cpu_all(dev);
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}
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EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
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void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
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size_t size, enum dma_data_direction dir, unsigned long attrs)
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{
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phys_addr_t phys = dma_to_phys(dev, addr);
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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dma_direct_sync_single_for_cpu(dev, addr, size, dir);
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if (unlikely(is_swiotlb_buffer(phys)))
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swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
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}
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EXPORT_SYMBOL(dma_direct_unmap_page);
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void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
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attrs);
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}
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EXPORT_SYMBOL(dma_direct_unmap_sg);
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#endif
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static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
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size_t size)
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{
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return swiotlb_force != SWIOTLB_FORCE &&
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(!dev || dma_capable(dev, dma_addr, size));
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}
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dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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phys_addr_t phys = page_to_phys(page) + offset;
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dma_addr_t dma_addr = phys_to_dma(dev, phys);
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if (unlikely(!dma_direct_possible(dev, dma_addr, size)) &&
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!swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) {
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report_addr(dev, dma_addr, size);
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return DMA_MAPPING_ERROR;
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}
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if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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arch_sync_dma_for_device(dev, phys, size, dir);
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return dma_addr;
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}
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EXPORT_SYMBOL(dma_direct_map_page);
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int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
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enum dma_data_direction dir, unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sgl, sg, nents, i) {
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sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
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sg->offset, sg->length, dir, attrs);
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if (sg->dma_address == DMA_MAPPING_ERROR)
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goto out_unmap;
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sg_dma_len(sg) = sg->length;
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}
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return nents;
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out_unmap:
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dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
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return 0;
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}
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EXPORT_SYMBOL(dma_direct_map_sg);
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dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir, unsigned long attrs)
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{
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dma_addr_t dma_addr = paddr;
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if (unlikely(!dma_direct_possible(dev, dma_addr, size))) {
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report_addr(dev, dma_addr, size);
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return DMA_MAPPING_ERROR;
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}
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return dma_addr;
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}
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EXPORT_SYMBOL(dma_direct_map_resource);
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/*
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* Because 32-bit DMA masks are so common we expect every architecture to be
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* able to satisfy them - either by not supporting more physical memory, or by
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* providing a ZONE_DMA32. If neither is the case, the architecture needs to
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* use an IOMMU instead of the direct mapping.
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*/
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int dma_direct_supported(struct device *dev, u64 mask)
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{
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u64 min_mask;
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if (IS_ENABLED(CONFIG_ZONE_DMA))
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min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
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else
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min_mask = DMA_BIT_MASK(32);
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min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
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/*
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* This check needs to be against the actual bit mask value, so
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* use __phys_to_dma() here so that the SME encryption mask isn't
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* part of the check.
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*/
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return mask >= __phys_to_dma(dev, min_mask);
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}
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size_t dma_direct_max_mapping_size(struct device *dev)
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{
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size_t size = SIZE_MAX;
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/* If SWIOTLB is active, use its maximum mapping size */
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if (is_swiotlb_active())
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size = swiotlb_max_mapping_size(dev);
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return size;
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}
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