256 lines
6.5 KiB
C
256 lines
6.5 KiB
C
/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DEVICE_INFO_H_
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#define _INTEL_DEVICE_INFO_H_
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#include "intel_display.h"
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struct drm_printer;
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struct drm_i915_private;
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/* Keep in gen based order, and chronological order within a gen */
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enum intel_platform {
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INTEL_PLATFORM_UNINITIALIZED = 0,
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/* gen2 */
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INTEL_I830,
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INTEL_I845G,
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INTEL_I85X,
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INTEL_I865G,
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/* gen3 */
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INTEL_I915G,
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INTEL_I915GM,
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INTEL_I945G,
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INTEL_I945GM,
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INTEL_G33,
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INTEL_PINEVIEW,
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/* gen4 */
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INTEL_I965G,
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INTEL_I965GM,
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INTEL_G45,
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INTEL_GM45,
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/* gen5 */
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INTEL_IRONLAKE,
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/* gen6 */
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INTEL_SANDYBRIDGE,
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/* gen7 */
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INTEL_IVYBRIDGE,
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INTEL_VALLEYVIEW,
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INTEL_HASWELL,
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/* gen8 */
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INTEL_BROADWELL,
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INTEL_CHERRYVIEW,
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/* gen9 */
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INTEL_SKYLAKE,
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INTEL_BROXTON,
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INTEL_KABYLAKE,
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INTEL_GEMINILAKE,
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INTEL_COFFEELAKE,
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/* gen10 */
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INTEL_CANNONLAKE,
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/* gen11 */
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INTEL_ICELAKE,
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INTEL_MAX_PLATFORMS
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};
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#define DEV_INFO_FOR_EACH_FLAG(func) \
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func(is_mobile); \
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func(is_lp); \
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func(is_alpha_support); \
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/* Keep has_* in alphabetical order */ \
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func(has_64bit_reloc); \
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func(has_aliasing_ppgtt); \
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func(has_csr); \
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func(has_ddi); \
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func(has_dp_mst); \
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func(has_reset_engine); \
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func(has_fbc); \
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func(has_fpga_dbg); \
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func(has_full_ppgtt); \
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func(has_full_48bit_ppgtt); \
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func(has_gmch_display); \
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func(has_guc); \
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func(has_guc_ct); \
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func(has_hotplug); \
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func(has_l3_dpf); \
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func(has_llc); \
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func(has_logical_ring_contexts); \
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func(has_logical_ring_elsq); \
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func(has_logical_ring_preemption); \
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func(has_overlay); \
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func(has_pooled_eu); \
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func(has_psr); \
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func(has_rc6); \
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func(has_rc6p); \
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func(has_resource_streamer); \
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func(has_runtime_pm); \
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func(has_snoop); \
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func(unfenced_needs_alignment); \
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func(cursor_needs_physical); \
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func(hws_needs_physical); \
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func(overlay_needs_physical); \
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func(supports_tv); \
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func(has_ipc);
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#define GEN_MAX_SLICES (6) /* CNL upper bound */
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#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
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struct sseu_dev_info {
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u8 slice_mask;
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u8 subslice_mask[GEN_MAX_SUBSLICES];
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u16 eu_total;
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u8 eu_per_subslice;
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u8 min_eu_in_pool;
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/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
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u8 subslice_7eu[3];
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u8 has_slice_pg:1;
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u8 has_subslice_pg:1;
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u8 has_eu_pg:1;
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/* Topology fields */
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u8 max_slices;
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u8 max_subslices;
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u8 max_eus_per_subslice;
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/* We don't have more than 8 eus per subslice at the moment and as we
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* store eus enabled using bits, no need to multiply by eus per
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* subslice.
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*/
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u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
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};
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typedef u8 intel_ring_mask_t;
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struct intel_device_info {
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u16 device_id;
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u16 gen_mask;
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u8 gen;
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u8 gt; /* GT number, 0 if undefined */
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u8 num_rings;
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intel_ring_mask_t ring_mask; /* Rings supported by the HW */
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enum intel_platform platform;
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u32 platform_mask;
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unsigned int page_sizes; /* page sizes supported by the HW */
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u32 display_mmio_offset;
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u8 num_pipes;
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u8 num_sprites[I915_MAX_PIPES];
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u8 num_scalers[I915_MAX_PIPES];
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#define DEFINE_FLAG(name) u8 name:1
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DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
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#undef DEFINE_FLAG
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u16 ddb_size; /* in blocks */
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/* Register offsets for the various display pipes and transcoders */
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int pipe_offsets[I915_MAX_TRANSCODERS];
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int trans_offsets[I915_MAX_TRANSCODERS];
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int palette_offsets[I915_MAX_PIPES];
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int cursor_offsets[I915_MAX_PIPES];
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/* Slice/subslice/EU info */
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struct sseu_dev_info sseu;
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u32 cs_timestamp_frequency_khz;
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struct color_luts {
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u16 degamma_lut_size;
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u16 gamma_lut_size;
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} color;
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};
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struct intel_driver_caps {
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unsigned int scheduler;
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};
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static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
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{
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unsigned int i, total = 0;
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for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
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total += hweight8(sseu->subslice_mask[i]);
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return total;
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}
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static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
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int slice, int subslice)
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{
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int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
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BITS_PER_BYTE);
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int slice_stride = sseu->max_subslices * subslice_stride;
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return slice * slice_stride + subslice * subslice_stride;
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}
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static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
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int slice, int subslice)
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{
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int i, offset = sseu_eu_idx(sseu, slice, subslice);
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u16 eu_mask = 0;
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for (i = 0;
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i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
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eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
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(i * BITS_PER_BYTE);
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}
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return eu_mask;
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}
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static inline void sseu_set_eus(struct sseu_dev_info *sseu,
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int slice, int subslice, u16 eu_mask)
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{
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int i, offset = sseu_eu_idx(sseu, slice, subslice);
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for (i = 0;
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i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
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sseu->eu_mask[offset + i] =
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(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
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}
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}
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const char *intel_platform_name(enum intel_platform platform);
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void intel_device_info_runtime_init(struct intel_device_info *info);
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void intel_device_info_dump(const struct intel_device_info *info,
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struct drm_printer *p);
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void intel_device_info_dump_flags(const struct intel_device_info *info,
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struct drm_printer *p);
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void intel_device_info_dump_runtime(const struct intel_device_info *info,
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struct drm_printer *p);
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void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
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struct drm_printer *p);
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void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
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void intel_driver_caps_print(const struct intel_driver_caps *caps,
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struct drm_printer *p);
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#endif
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