455 lines
11 KiB
C
455 lines
11 KiB
C
/*
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* Tegra host1x driver
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*
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/host1x.h>
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#undef CREATE_TRACE_POINTS
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#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
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#include <asm/dma-iommu.h>
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#endif
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#include "bus.h"
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#include "channel.h"
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#include "debug.h"
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#include "dev.h"
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#include "intr.h"
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#include "hw/host1x01.h"
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#include "hw/host1x02.h"
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#include "hw/host1x04.h"
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#include "hw/host1x05.h"
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#include "hw/host1x06.h"
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#include "hw/host1x07.h"
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void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
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{
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writel(v, host1x->hv_regs + r);
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}
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u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
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{
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return readl(host1x->hv_regs + r);
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}
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void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
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{
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void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
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writel(v, sync_regs + r);
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}
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u32 host1x_sync_readl(struct host1x *host1x, u32 r)
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{
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void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
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return readl(sync_regs + r);
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}
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void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
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{
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writel(v, ch->regs + r);
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}
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u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
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{
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return readl(ch->regs + r);
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}
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static const struct host1x_info host1x01_info = {
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.nb_channels = 8,
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.nb_pts = 32,
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.nb_mlocks = 16,
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.nb_bases = 8,
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.init = host1x01_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x02_info = {
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.nb_channels = 9,
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.nb_pts = 32,
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.nb_mlocks = 16,
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.nb_bases = 12,
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.init = host1x02_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x04_info = {
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.nb_channels = 12,
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.nb_pts = 192,
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.nb_mlocks = 16,
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.nb_bases = 64,
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.init = host1x04_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static const struct host1x_info host1x05_info = {
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.nb_channels = 14,
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.nb_pts = 192,
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.nb_mlocks = 16,
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.nb_bases = 64,
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.init = host1x05_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static const struct host1x_sid_entry tegra186_sid_table[] = {
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{
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/* VIC */
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.base = 0x1af0,
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.offset = 0x30,
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.limit = 0x34
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},
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};
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static const struct host1x_info host1x06_info = {
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.nb_channels = 63,
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.nb_pts = 576,
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.nb_mlocks = 24,
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.nb_bases = 16,
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.init = host1x06_init,
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.sync_offset = 0x0,
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.dma_mask = DMA_BIT_MASK(40),
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.has_hypervisor = true,
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.num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
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.sid_table = tegra186_sid_table,
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};
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static const struct host1x_sid_entry tegra194_sid_table[] = {
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{
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/* VIC */
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.base = 0x1af0,
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.offset = 0x30,
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.limit = 0x34
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},
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};
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static const struct host1x_info host1x07_info = {
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.nb_channels = 63,
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.nb_pts = 704,
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.nb_mlocks = 32,
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.nb_bases = 0,
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.init = host1x07_init,
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.sync_offset = 0x0,
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.dma_mask = DMA_BIT_MASK(40),
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.has_hypervisor = true,
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.num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
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.sid_table = tegra194_sid_table,
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};
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static const struct of_device_id host1x_of_match[] = {
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{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
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{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
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{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
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{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
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{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
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{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
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{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, host1x_of_match);
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static void host1x_setup_sid_table(struct host1x *host)
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{
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const struct host1x_info *info = host->info;
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unsigned int i;
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for (i = 0; i < info->num_sid_entries; i++) {
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const struct host1x_sid_entry *entry = &info->sid_table[i];
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host1x_hypervisor_writel(host, entry->offset, entry->base);
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host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
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}
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}
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static int host1x_probe(struct platform_device *pdev)
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{
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struct host1x *host;
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struct resource *regs, *hv_regs = NULL;
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int syncpt_irq;
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int err;
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host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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host->info = of_device_get_match_data(&pdev->dev);
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if (host->info->has_hypervisor) {
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regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
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if (!regs) {
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dev_err(&pdev->dev, "failed to get vm registers\n");
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return -ENXIO;
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}
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hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"hypervisor");
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if (!hv_regs) {
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dev_err(&pdev->dev,
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"failed to get hypervisor registers\n");
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return -ENXIO;
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}
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} else {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs) {
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dev_err(&pdev->dev, "failed to get registers\n");
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return -ENXIO;
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}
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}
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syncpt_irq = platform_get_irq(pdev, 0);
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if (syncpt_irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
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return syncpt_irq;
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}
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mutex_init(&host->devices_lock);
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INIT_LIST_HEAD(&host->devices);
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INIT_LIST_HEAD(&host->list);
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host->dev = &pdev->dev;
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/* set common host1x device data */
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platform_set_drvdata(pdev, host);
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host->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(host->regs))
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return PTR_ERR(host->regs);
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if (host->info->has_hypervisor) {
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host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
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if (IS_ERR(host->hv_regs))
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return PTR_ERR(host->hv_regs);
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}
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dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
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if (host->info->init) {
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err = host->info->init(host);
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if (err)
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return err;
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}
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host->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(host->clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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err = PTR_ERR(host->clk);
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return err;
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}
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host->rst = devm_reset_control_get(&pdev->dev, "host1x");
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if (IS_ERR(host->rst)) {
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err = PTR_ERR(host->rst);
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dev_err(&pdev->dev, "failed to get reset: %d\n", err);
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return err;
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}
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#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
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if (host->dev->archdata.mapping) {
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struct dma_iommu_mapping *mapping =
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to_dma_iommu_mapping(host->dev);
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arm_iommu_detach_device(host->dev);
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arm_iommu_release_mapping(mapping);
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}
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#endif
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if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
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goto skip_iommu;
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host->group = iommu_group_get(&pdev->dev);
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if (host->group) {
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struct iommu_domain_geometry *geometry;
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u64 mask = dma_get_mask(host->dev);
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dma_addr_t start, end;
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unsigned long order;
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err = iova_cache_get();
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if (err < 0)
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goto put_group;
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host->domain = iommu_domain_alloc(&platform_bus_type);
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if (!host->domain) {
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err = -ENOMEM;
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goto put_cache;
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}
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err = iommu_attach_group(host->domain, host->group);
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if (err) {
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if (err == -ENODEV) {
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iommu_domain_free(host->domain);
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host->domain = NULL;
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iova_cache_put();
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iommu_group_put(host->group);
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host->group = NULL;
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goto skip_iommu;
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}
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goto fail_free_domain;
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}
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geometry = &host->domain->geometry;
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start = geometry->aperture_start & mask;
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end = geometry->aperture_end & mask;
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order = __ffs(host->domain->pgsize_bitmap);
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init_iova_domain(&host->iova, 1UL << order, start >> order);
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host->iova_end = end;
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}
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skip_iommu:
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err = host1x_channel_list_init(&host->channel_list,
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host->info->nb_channels);
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if (err) {
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dev_err(&pdev->dev, "failed to initialize channel list\n");
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goto fail_detach_device;
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}
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err = clk_prepare_enable(host->clk);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to enable clock\n");
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goto fail_free_channels;
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}
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err = reset_control_deassert(host->rst);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
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goto fail_unprepare_disable;
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}
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err = host1x_syncpt_init(host);
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if (err) {
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dev_err(&pdev->dev, "failed to initialize syncpts\n");
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goto fail_reset_assert;
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}
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err = host1x_intr_init(host, syncpt_irq);
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if (err) {
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dev_err(&pdev->dev, "failed to initialize interrupts\n");
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goto fail_deinit_syncpt;
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}
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host1x_debug_init(host);
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if (host->info->has_hypervisor)
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host1x_setup_sid_table(host);
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err = host1x_register(host);
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if (err < 0)
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goto fail_deinit_intr;
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return 0;
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fail_deinit_intr:
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host1x_intr_deinit(host);
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fail_deinit_syncpt:
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host1x_syncpt_deinit(host);
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fail_reset_assert:
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reset_control_assert(host->rst);
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fail_unprepare_disable:
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clk_disable_unprepare(host->clk);
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fail_free_channels:
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host1x_channel_list_free(&host->channel_list);
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fail_detach_device:
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if (host->group && host->domain) {
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put_iova_domain(&host->iova);
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iommu_detach_group(host->domain, host->group);
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}
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fail_free_domain:
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if (host->domain)
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iommu_domain_free(host->domain);
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put_cache:
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if (host->group)
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iova_cache_put();
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put_group:
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iommu_group_put(host->group);
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return err;
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}
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static int host1x_remove(struct platform_device *pdev)
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{
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struct host1x *host = platform_get_drvdata(pdev);
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host1x_unregister(host);
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host1x_intr_deinit(host);
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host1x_syncpt_deinit(host);
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reset_control_assert(host->rst);
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clk_disable_unprepare(host->clk);
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if (host->domain) {
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put_iova_domain(&host->iova);
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iommu_detach_group(host->domain, host->group);
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iommu_domain_free(host->domain);
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iova_cache_put();
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iommu_group_put(host->group);
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}
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return 0;
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}
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static struct platform_driver tegra_host1x_driver = {
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.driver = {
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.name = "tegra-host1x",
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.of_match_table = host1x_of_match,
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},
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.probe = host1x_probe,
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.remove = host1x_remove,
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};
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static struct platform_driver * const drivers[] = {
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&tegra_host1x_driver,
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&tegra_mipi_driver,
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};
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static int __init tegra_host1x_init(void)
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{
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int err;
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err = bus_register(&host1x_bus_type);
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if (err < 0)
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return err;
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err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
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if (err < 0)
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bus_unregister(&host1x_bus_type);
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return err;
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}
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module_init(tegra_host1x_init);
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static void __exit tegra_host1x_exit(void)
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{
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platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
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bus_unregister(&host1x_bus_type);
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}
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module_exit(tegra_host1x_exit);
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MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
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MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
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MODULE_DESCRIPTION("Host1x driver for Tegra products");
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MODULE_LICENSE("GPL");
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