140 lines
3.3 KiB
C
140 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017-2018 SiFive
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* Copyright (C) 2020 Western Digital Corporation or its affiliates.
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*/
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#define pr_fmt(fmt) "riscv-intc: " fmt
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#include <linux/atomic.h>
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#include <linux/bits.h>
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#include <linux/cpu.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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static struct irq_domain *intc_domain;
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static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
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{
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unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
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if (unlikely(cause >= BITS_PER_LONG))
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panic("unexpected interrupt cause");
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switch (cause) {
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#ifdef CONFIG_SMP
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case RV_IRQ_SOFT:
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/*
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* We only use software interrupts to pass IPIs, so if a
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* non-SMP system gets one, then we don't know what to do.
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*/
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handle_IPI(regs);
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break;
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#endif
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default:
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generic_handle_domain_irq(intc_domain, cause);
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break;
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}
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}
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/*
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* On RISC-V systems local interrupts are masked or unmasked by writing
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* the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written
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* on the local hart, these functions can only be called on the hart that
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* corresponds to the IRQ chip.
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*/
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static void riscv_intc_irq_mask(struct irq_data *d)
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{
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csr_clear(CSR_IE, BIT(d->hwirq));
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}
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static void riscv_intc_irq_unmask(struct irq_data *d)
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{
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csr_set(CSR_IE, BIT(d->hwirq));
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}
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static int riscv_intc_cpu_starting(unsigned int cpu)
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{
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csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
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return 0;
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}
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static int riscv_intc_cpu_dying(unsigned int cpu)
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{
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csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
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return 0;
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}
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static struct irq_chip riscv_intc_chip = {
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.name = "RISC-V INTC",
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.irq_mask = riscv_intc_irq_mask,
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.irq_unmask = riscv_intc_irq_unmask,
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};
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static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_percpu_devid(irq);
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irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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return 0;
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}
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static const struct irq_domain_ops riscv_intc_domain_ops = {
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.map = riscv_intc_domain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init riscv_intc_init(struct device_node *node,
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struct device_node *parent)
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{
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int rc;
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unsigned long hartid;
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rc = riscv_of_parent_hartid(node, &hartid);
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if (rc < 0) {
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pr_warn("unable to find hart id for %pOF\n", node);
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return 0;
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}
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/*
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* The DT will have one INTC DT node under each CPU (or HART)
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* DT node so riscv_intc_init() function will be called once
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* for each INTC DT node. We only need to do INTC initialization
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* for the INTC DT node belonging to boot CPU (or boot HART).
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*/
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if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
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return 0;
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intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
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&riscv_intc_domain_ops, NULL);
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if (!intc_domain) {
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pr_err("unable to add IRQ domain\n");
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return -ENXIO;
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}
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rc = set_handle_irq(&riscv_intc_irq);
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if (rc) {
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pr_err("failed to set irq handler\n");
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return rc;
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}
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cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
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"irqchip/riscv/intc:starting",
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riscv_intc_cpu_starting,
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riscv_intc_cpu_dying);
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pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
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return 0;
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}
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IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
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