285 lines
6.6 KiB
C
285 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/A1 IRQC Driver
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*
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* Copyright (C) 2019 Glider bvba
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define IRQC_NUM_IRQ 8
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#define ICR0 0 /* Interrupt Control Register 0 */
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#define ICR0_NMIL BIT(15) /* NMI Input Level (0=low, 1=high) */
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#define ICR0_NMIE BIT(8) /* Edge Select (0=falling, 1=rising) */
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#define ICR0_NMIF BIT(1) /* NMI Interrupt Request */
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#define ICR1 2 /* Interrupt Control Register 1 */
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#define ICR1_IRQS(n, sense) ((sense) << ((n) * 2)) /* IRQ Sense Select */
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#define ICR1_IRQS_LEVEL_LOW 0
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#define ICR1_IRQS_EDGE_FALLING 1
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#define ICR1_IRQS_EDGE_RISING 2
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#define ICR1_IRQS_EDGE_BOTH 3
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#define ICR1_IRQS_MASK(n) ICR1_IRQS((n), 3)
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#define IRQRR 4 /* IRQ Interrupt Request Register */
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struct rza1_irqc_priv {
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struct device *dev;
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void __iomem *base;
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struct irq_chip chip;
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struct irq_domain *irq_domain;
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struct of_phandle_args map[IRQC_NUM_IRQ];
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};
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static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data)
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{
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return data->domain->host_data;
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}
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static void rza1_irqc_eoi(struct irq_data *d)
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{
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struct rza1_irqc_priv *priv = irq_data_to_priv(d);
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u16 bit = BIT(irqd_to_hwirq(d));
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u16 tmp;
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tmp = readw_relaxed(priv->base + IRQRR);
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if (tmp & bit)
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writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
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priv->base + IRQRR);
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irq_chip_eoi_parent(d);
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}
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static int rza1_irqc_set_type(struct irq_data *d, unsigned int type)
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{
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struct rza1_irqc_priv *priv = irq_data_to_priv(d);
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unsigned int hw_irq = irqd_to_hwirq(d);
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u16 sense, tmp;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_LEVEL_LOW:
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sense = ICR1_IRQS_LEVEL_LOW;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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sense = ICR1_IRQS_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_RISING:
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sense = ICR1_IRQS_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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sense = ICR1_IRQS_EDGE_BOTH;
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break;
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default:
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return -EINVAL;
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}
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tmp = readw_relaxed(priv->base + ICR1);
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tmp &= ~ICR1_IRQS_MASK(hw_irq);
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tmp |= ICR1_IRQS(hw_irq, sense);
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writew_relaxed(tmp, priv->base + ICR1);
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return 0;
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}
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static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct rza1_irqc_priv *priv = domain->host_data;
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struct irq_fwspec *fwspec = arg;
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unsigned int hwirq = fwspec->param[0];
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struct irq_fwspec spec;
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unsigned int i;
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int ret;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
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priv);
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if (ret)
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return ret;
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spec.fwnode = &priv->dev->of_node->fwnode;
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spec.param_count = priv->map[hwirq].args_count;
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for (i = 0; i < spec.param_count; i++)
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spec.param[i] = priv->map[hwirq].args[i];
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec);
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}
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static int rza1_irqc_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec, unsigned long *hwirq,
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unsigned int *type)
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{
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if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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static const struct irq_domain_ops rza1_irqc_domain_ops = {
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.alloc = rza1_irqc_alloc,
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.translate = rza1_irqc_translate,
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};
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static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv,
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struct device_node *gic_node)
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{
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unsigned int imaplen, i, j, ret;
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struct device *dev = priv->dev;
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struct device_node *ipar;
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const __be32 *imap;
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u32 intsize;
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imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);
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if (!imap)
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return -EINVAL;
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for (i = 0; i < IRQC_NUM_IRQ; i++) {
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if (imaplen < 3)
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return -EINVAL;
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/* Check interrupt number, ignore sense */
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if (be32_to_cpup(imap) != i)
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return -EINVAL;
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ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2));
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if (ipar != gic_node) {
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of_node_put(ipar);
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return -EINVAL;
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}
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imap += 3;
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imaplen -= 3;
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ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
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of_node_put(ipar);
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if (ret)
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return ret;
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if (imaplen < intsize)
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return -EINVAL;
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priv->map[i].args_count = intsize;
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for (j = 0; j < intsize; j++)
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priv->map[i].args[j] = be32_to_cpup(imap++);
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imaplen -= intsize;
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}
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return 0;
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}
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static int rza1_irqc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct irq_domain *parent = NULL;
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struct device_node *gic_node;
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struct rza1_irqc_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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priv->dev = dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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gic_node = of_irq_find_parent(np);
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if (gic_node)
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parent = irq_find_host(gic_node);
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if (!parent) {
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dev_err(dev, "cannot find parent domain\n");
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ret = -ENODEV;
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goto out_put_node;
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}
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ret = rza1_irqc_parse_map(priv, gic_node);
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if (ret) {
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dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);
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goto out_put_node;
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}
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priv->chip.name = "rza1-irqc";
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priv->chip.irq_mask = irq_chip_mask_parent;
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priv->chip.irq_unmask = irq_chip_unmask_parent;
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priv->chip.irq_eoi = rza1_irqc_eoi;
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priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy;
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priv->chip.irq_set_type = rza1_irqc_set_type;
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priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
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priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
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np, &rza1_irqc_domain_ops,
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priv);
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if (!priv->irq_domain) {
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dev_err(dev, "cannot initialize irq domain\n");
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ret = -ENOMEM;
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}
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out_put_node:
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of_node_put(gic_node);
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return ret;
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}
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static int rza1_irqc_remove(struct platform_device *pdev)
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{
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struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
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irq_domain_remove(priv->irq_domain);
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return 0;
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}
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static const struct of_device_id rza1_irqc_dt_ids[] = {
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{ .compatible = "renesas,rza1-irqc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
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static struct platform_driver rza1_irqc_device_driver = {
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.probe = rza1_irqc_probe,
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.remove = rza1_irqc_remove,
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.driver = {
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.name = "renesas_rza1_irqc",
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.of_match_table = rza1_irqc_dt_ids,
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}
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};
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static int __init rza1_irqc_init(void)
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{
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return platform_driver_register(&rza1_irqc_device_driver);
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}
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postcore_initcall(rza1_irqc_init);
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static void __exit rza1_irqc_exit(void)
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{
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platform_driver_unregister(&rza1_irqc_device_driver);
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}
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module_exit(rza1_irqc_exit);
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MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
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MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver");
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MODULE_LICENSE("GPL v2");
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