139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* All RISC-V systems have a timer attached to every hart. These timers can
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* either be read from the "time" and "timeh" CSRs, and can use the SBI to
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* setup events, or directly accessed using MMIO registers.
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/sched_clock.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <asm/smp.h>
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#include <asm/sbi.h>
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u64 __iomem *riscv_time_cmp;
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u64 __iomem *riscv_time_val;
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static inline void mmio_set_timer(u64 val)
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{
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void __iomem *r;
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r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
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writeq_relaxed(val, r);
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}
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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csr_set(CSR_IE, IE_TIE);
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_set_timer(get_cycles64() + delta);
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else
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mmio_set_timer(get_cycles64() + delta);
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return 0;
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}
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static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
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.name = "riscv_timer_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 100,
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.set_next_event = riscv_clock_next_event,
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};
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/*
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* It is guaranteed that all the timers across all the harts are synchronized
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* within one tick of each other, so while this could technically go
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* backwards when hopping between CPUs, practically it won't happen.
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*/
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static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
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{
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return get_cycles64();
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}
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static u64 riscv_sched_clock(void)
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{
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return get_cycles64();
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}
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static struct clocksource riscv_clocksource = {
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.name = "riscv_clocksource",
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.rating = 300,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = riscv_clocksource_rdtime,
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};
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static int riscv_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
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ce->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
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csr_set(CSR_IE, IE_TIE);
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return 0;
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}
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static int riscv_timer_dying_cpu(unsigned int cpu)
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{
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csr_clear(CSR_IE, IE_TIE);
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return 0;
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}
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/* called directly from the low-level interrupt handler */
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void riscv_timer_interrupt(void)
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{
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struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
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csr_clear(CSR_IE, IE_TIE);
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evdev->event_handler(evdev);
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}
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static int __init riscv_timer_init_dt(struct device_node *n)
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{
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int cpuid, hartid, error;
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hartid = riscv_of_processor_hartid(n);
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if (hartid < 0) {
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pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
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n, hartid);
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return hartid;
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}
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cpuid = riscv_hartid_to_cpuid(hartid);
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if (cpuid < 0) {
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pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
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return cpuid;
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}
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if (cpuid != smp_processor_id())
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return 0;
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pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
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__func__, cpuid, hartid);
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error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
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if (error) {
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pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
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error, cpuid);
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return error;
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}
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sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
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error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
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"clockevents/riscv/timer:starting",
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riscv_timer_starting_cpu, riscv_timer_dying_cpu);
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if (error)
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pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
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error);
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return error;
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}
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TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
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