478 lines
13 KiB
C
478 lines
13 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "cikd.h"
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#include "bif/bif_4_1_d.h"
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#include "bif/bif_4_1_sh_mask.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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/*
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* Interrupts
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* Starting with r6xx, interrupts are handled via a ring buffer.
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* Ring buffers are areas of GPU accessible memory that the GPU
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* writes interrupt vectors into and the host reads vectors out of.
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* There is a rptr (read pointer) that determines where the
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* host is currently reading, and a wptr (write pointer)
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* which determines where the GPU has written. When the
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* pointers are equal, the ring is idle. When the GPU
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* writes vectors to the ring buffer, it increments the
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* wptr. When there is an interrupt, the host then starts
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* fetching commands and processing them until the pointers are
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* equal again at which point it updates the rptr.
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*/
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static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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/**
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* cik_ih_enable_interrupts - Enable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Enable the interrupt ring buffer (CIK).
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*/
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static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_cntl = RREG32(mmIH_CNTL);
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u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
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ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
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ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
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WREG32(mmIH_CNTL, ih_cntl);
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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adev->irq.ih.enabled = true;
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}
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/**
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* cik_ih_disable_interrupts - Disable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Disable the interrupt ring buffer (CIK).
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*/
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static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
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u32 ih_cntl = RREG32(mmIH_CNTL);
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ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
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ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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WREG32(mmIH_CNTL, ih_cntl);
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/* set rptr, wptr to 0 */
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WREG32(mmIH_RB_RPTR, 0);
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WREG32(mmIH_RB_WPTR, 0);
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adev->irq.ih.enabled = false;
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adev->irq.ih.rptr = 0;
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}
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/**
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* cik_ih_irq_init - init and enable the interrupt ring
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate a ring buffer for the interrupt controller,
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* enable the RLC, disable interrupts, enable the IH
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* ring buffer and enable it (CIK).
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* Called at device load and reume.
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* Returns 0 for success, errors for failure.
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*/
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static int cik_ih_irq_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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int rb_bufsz;
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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u64 wptr_off;
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/* disable irqs */
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cik_ih_disable_interrupts(adev);
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/* setup interrupt control */
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WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
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interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
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/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
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WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
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WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
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IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
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(rb_bufsz << 1));
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ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
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/* set the writeback address whether it's enabled or not */
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wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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/* set rptr, wptr to 0 */
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WREG32(mmIH_RB_RPTR, 0);
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WREG32(mmIH_RB_WPTR, 0);
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/* Default settings for IH_CNTL (disabled at first) */
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ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
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(0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
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(0 << IH_CNTL__MC_VMID__SHIFT);
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/* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
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if (adev->irq.msi_enabled)
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ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
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WREG32(mmIH_CNTL, ih_cntl);
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pci_set_master(adev->pdev);
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/* enable irqs */
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cik_ih_enable_interrupts(adev);
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return ret;
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}
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/**
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* cik_ih_irq_disable - disable interrupts
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*
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* @adev: amdgpu_device pointer
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*
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* Disable interrupts on the hw (CIK).
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*/
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static void cik_ih_irq_disable(struct amdgpu_device *adev)
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{
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cik_ih_disable_interrupts(adev);
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/* Wait and acknowledge irq */
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mdelay(1);
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}
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/**
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* cik_ih_get_wptr - get the IH ring buffer wptr
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*
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* @adev: amdgpu_device pointer
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*
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* Get the IH ring buffer wptr from either the register
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* or the writeback memory buffer (CIK). Also check for
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* ring buffer overflow and deal with it.
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* Used by cik_irq_process().
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* Returns the value of the wptr.
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*/
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static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
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{
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u32 wptr, tmp;
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wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
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wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
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/* When a ring buffer overflow happen start parsing interrupt
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* from the last not overwritten vector (wptr + 16). Hopefully
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* this should allow us to catchup.
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*/
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dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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tmp = RREG32(mmIH_RB_CNTL);
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tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(mmIH_RB_CNTL, tmp);
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}
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return (wptr & adev->irq.ih.ptr_mask);
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}
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/* CIK IV Ring
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* Each IV ring entry is 128 bits:
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* [7:0] - interrupt source id
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* [31:8] - reserved
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* [59:32] - interrupt source data
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* [63:60] - reserved
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* [71:64] - RINGID
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* CP:
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* ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
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* QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
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* - for gfx, hw shader state (0=PS...5=LS, 6=CS)
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* ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
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* PIPE_ID - ME0 0=3D
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* - ME1&2 compute dispatcher (4 pipes each)
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* SDMA:
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* INSTANCE_ID [1:0], QUEUE_ID[1:0]
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* INSTANCE_ID - 0 = sdma0, 1 = sdma1
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* QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
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* [79:72] - VMID
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* [95:80] - PASID
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* [127:96] - reserved
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*/
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/**
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* cik_ih_decode_iv - decode an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Decodes the interrupt vector at the current rptr
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* position and also advance the position.
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*/
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static void cik_ih_decode_iv(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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/* wptr/rptr are in bytes! */
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u32 ring_index = adev->irq.ih.rptr >> 2;
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uint32_t dw[4];
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dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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entry->src_id = dw[0] & 0xff;
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entry->src_data = dw[1] & 0xfffffff;
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entry->ring_id = dw[2] & 0xff;
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entry->vm_id = (dw[2] >> 8) & 0xff;
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entry->pas_id = (dw[2] >> 16) & 0xffff;
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/* wptr/rptr are in bytes! */
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adev->irq.ih.rptr += 16;
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}
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/**
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* cik_ih_set_rptr - set the IH ring buffer rptr
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*
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* @adev: amdgpu_device pointer
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*
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* Set the IH ring buffer rptr.
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*/
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static void cik_ih_set_rptr(struct amdgpu_device *adev)
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{
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WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
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}
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static int cik_ih_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret;
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ret = amdgpu_irq_add_domain(adev);
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if (ret)
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return ret;
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cik_ih_set_interrupt_funcs(adev);
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return 0;
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}
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static int cik_ih_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
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if (r)
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return r;
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r = amdgpu_irq_init(adev);
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return r;
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}
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static int cik_ih_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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amdgpu_irq_remove_domain(adev);
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return 0;
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}
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static int cik_ih_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = cik_ih_irq_init(adev);
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if (r)
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return r;
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return 0;
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}
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static int cik_ih_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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cik_ih_irq_disable(adev);
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return 0;
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}
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static int cik_ih_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return cik_ih_hw_fini(adev);
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}
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static int cik_ih_resume(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return cik_ih_hw_init(adev);
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}
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static bool cik_ih_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 tmp = RREG32(mmSRBM_STATUS);
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if (tmp & SRBM_STATUS__IH_BUSY_MASK)
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return false;
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return true;
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}
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static int cik_ih_wait_for_idle(void *handle)
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{
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unsigned i;
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u32 tmp;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < adev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
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if (!tmp)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static void cik_ih_print_status(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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dev_info(adev->dev, "CIK IH registers\n");
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dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(mmSRBM_STATUS));
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dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(mmSRBM_STATUS2));
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dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
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RREG32(mmINTERRUPT_CNTL));
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dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
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RREG32(mmINTERRUPT_CNTL2));
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dev_info(adev->dev, " IH_CNTL=0x%08X\n",
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RREG32(mmIH_CNTL));
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dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
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RREG32(mmIH_RB_CNTL));
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dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
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RREG32(mmIH_RB_BASE));
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dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
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RREG32(mmIH_RB_WPTR_ADDR_LO));
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dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
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RREG32(mmIH_RB_WPTR_ADDR_HI));
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dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
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RREG32(mmIH_RB_RPTR));
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dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
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RREG32(mmIH_RB_WPTR));
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}
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static int cik_ih_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 srbm_soft_reset = 0;
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u32 tmp = RREG32(mmSRBM_STATUS);
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if (tmp & SRBM_STATUS__IH_BUSY_MASK)
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
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if (srbm_soft_reset) {
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cik_ih_print_status((void *)adev);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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cik_ih_print_status((void *)adev);
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}
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return 0;
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}
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static int cik_ih_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int cik_ih_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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return 0;
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}
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const struct amd_ip_funcs cik_ih_ip_funcs = {
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.early_init = cik_ih_early_init,
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.late_init = NULL,
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.sw_init = cik_ih_sw_init,
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.sw_fini = cik_ih_sw_fini,
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.hw_init = cik_ih_hw_init,
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.hw_fini = cik_ih_hw_fini,
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.suspend = cik_ih_suspend,
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.resume = cik_ih_resume,
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.is_idle = cik_ih_is_idle,
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.wait_for_idle = cik_ih_wait_for_idle,
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.soft_reset = cik_ih_soft_reset,
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.print_status = cik_ih_print_status,
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.set_clockgating_state = cik_ih_set_clockgating_state,
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.set_powergating_state = cik_ih_set_powergating_state,
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};
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|
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static const struct amdgpu_ih_funcs cik_ih_funcs = {
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.get_wptr = cik_ih_get_wptr,
|
|
.decode_iv = cik_ih_decode_iv,
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|
.set_rptr = cik_ih_set_rptr
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|
};
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|
|
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static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
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|
{
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|
if (adev->irq.ih_funcs == NULL)
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adev->irq.ih_funcs = &cik_ih_funcs;
|
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}
|