506 lines
18 KiB
C
506 lines
18 KiB
C
/*
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* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
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#define __LINUX_IRQCHIP_ARM_GIC_V3_H
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/*
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* Distributor registers. We assume we're running non-secure, with ARE
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* being set. Secure-only and non-ARE registers are not described.
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*/
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_STATUSR 0x0010
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#define GICD_SETSPI_NSR 0x0040
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#define GICD_CLRSPI_NSR 0x0048
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_SEIR 0x0068
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ISPENDR 0x0200
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#define GICD_ICPENDR 0x0280
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#define GICD_ISACTIVER 0x0300
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#define GICD_ICACTIVER 0x0380
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#define GICD_IPRIORITYR 0x0400
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#define GICD_ICFGR 0x0C00
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#define GICD_IGRPMODR 0x0D00
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#define GICD_NSACR 0x0E00
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#define GICD_IROUTER 0x6000
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#define GICD_IDREGS 0xFFD0
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#define GICD_PIDR2 0xFFE8
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/*
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* Those registers are actually from GICv2, but the spec demands that they
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* are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
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*/
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#define GICD_ITARGETSR 0x0800
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#define GICD_SGIR 0x0F00
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#define GICD_CPENDSGIR 0x0F10
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#define GICD_SPENDSGIR 0x0F20
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_DS (1U << 6)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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/*
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* In systems with a single security state (what we emulate in KVM)
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* the meaning of the interrupt group enable bits is slightly different
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*/
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#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
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#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
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#define GICD_TYPER_LPIS (1U << 17)
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#define GICD_TYPER_MBIS (1U << 16)
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#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
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#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
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#define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
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#define GIC_PIDR2_ARCH_MASK 0xf0
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#define GIC_PIDR2_ARCH_GICv3 0x30
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#define GIC_PIDR2_ARCH_GICv4 0x40
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#define GIC_V3_DIST_SIZE 0x10000
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/*
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* Re-Distributor registers, offsets from RD_base
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*/
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#define GICR_CTLR GICD_CTLR
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR GICD_STATUSR
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#define GICR_WAKER 0x0014
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#define GICR_SETLPIR 0x0040
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#define GICR_CLRLPIR 0x0048
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#define GICR_SEIR GICD_SEIR
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#define GICR_PROPBASER 0x0070
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#define GICR_PENDBASER 0x0078
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#define GICR_INVLPIR 0x00A0
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#define GICR_INVALLR 0x00B0
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#define GICR_SYNCR 0x00C0
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#define GICR_MOVLPIR 0x0100
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#define GICR_MOVALLR 0x0110
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#define GICR_IDREGS GICD_IDREGS
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
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#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GIC_BASER_CACHE_nCnB 0ULL
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#define GIC_BASER_CACHE_SameAsInner 0ULL
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#define GIC_BASER_CACHE_nC 1ULL
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#define GIC_BASER_CACHE_RaWt 2ULL
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#define GIC_BASER_CACHE_RaWb 3ULL
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#define GIC_BASER_CACHE_WaWt 4ULL
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#define GIC_BASER_CACHE_WaWb 5ULL
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#define GIC_BASER_CACHE_RaWaWt 6ULL
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#define GIC_BASER_CACHE_RaWaWb 7ULL
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#define GIC_BASER_CACHE_MASK 7ULL
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#define GIC_BASER_NonShareable 0ULL
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#define GIC_BASER_InnerShareable 1ULL
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#define GIC_BASER_OuterShareable 2ULL
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#define GIC_BASER_SHAREABILITY_MASK 3ULL
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#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
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(GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
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#define GIC_BASER_SHAREABILITY(reg, type) \
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(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
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/* encode a size field of width @w containing @n - 1 units */
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#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
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#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
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#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
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#define GICR_PROPBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
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#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
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#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
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#define GICR_PROPBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
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#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
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#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
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#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
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#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
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#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
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#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
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#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
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#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
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#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
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#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
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#define GICR_PENDBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
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#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
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#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
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#define GICR_PENDBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
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#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
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#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
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#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
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#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
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#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
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#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
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#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
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#define GICR_PENDBASER_PTZ BIT_ULL(62)
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/*
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* Re-Distributor registers, offsets from SGI_base
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*/
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#define GICR_IGROUPR0 GICD_IGROUPR
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#define GICR_ISENABLER0 GICD_ISENABLER
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#define GICR_ICENABLER0 GICD_ICENABLER
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#define GICR_ISPENDR0 GICD_ISPENDR
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#define GICR_ICPENDR0 GICD_ICPENDR
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#define GICR_ISACTIVER0 GICD_ISACTIVER
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#define GICR_ICACTIVER0 GICD_ICACTIVER
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#define GICR_IPRIORITYR0 GICD_IPRIORITYR
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#define GICR_ICFGR0 GICD_ICFGR
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#define GICR_IGRPMODR0 GICD_IGRPMODR
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#define GICR_NSACR GICD_NSACR
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_LAST (1U << 4)
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#define GIC_V3_REDIST_SIZE 0x20000
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#define LPI_PROP_GROUP1 (1 << 1)
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#define LPI_PROP_ENABLED (1 << 0)
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/*
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* ITS registers, offsets from ITS_base
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*/
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#define GITS_CTLR 0x0000
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#define GITS_IIDR 0x0004
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#define GITS_TYPER 0x0008
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#define GITS_CBASER 0x0080
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#define GITS_CWRITER 0x0088
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#define GITS_CREADR 0x0090
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#define GITS_BASER 0x0100
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#define GITS_IDREGS_BASE 0xffd0
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#define GITS_PIDR0 0xffe0
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#define GITS_PIDR1 0xffe4
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#define GITS_PIDR2 GICR_PIDR2
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#define GITS_PIDR4 0xffd0
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#define GITS_CIDR0 0xfff0
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#define GITS_CIDR1 0xfff4
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#define GITS_CIDR2 0xfff8
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#define GITS_CIDR3 0xfffc
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#define GITS_TRANSLATER 0x10040
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#define GITS_CTLR_ENABLE (1U << 0)
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#define GITS_CTLR_QUIESCENT (1U << 31)
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#define GITS_TYPER_PLPIS (1UL << 0)
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#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
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#define GITS_TYPER_IDBITS_SHIFT 8
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#define GITS_TYPER_DEVBITS_SHIFT 13
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#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
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#define GITS_TYPER_PTA (1UL << 19)
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#define GITS_TYPER_HWCOLLCNT_SHIFT 24
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#define GITS_IIDR_REV_SHIFT 12
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#define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
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#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
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#define GITS_IIDR_PRODUCTID_SHIFT 24
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#define GITS_CBASER_VALID (1ULL << 63)
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#define GITS_CBASER_SHAREABILITY_SHIFT (10)
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#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
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#define GITS_CBASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
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#define GITS_CBASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
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#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
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#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
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#define GITS_CBASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
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#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
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#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
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#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
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#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
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#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
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#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
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#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
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#define GITS_BASER_NR_REGS 8
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#define GITS_BASER_VALID (1ULL << 63)
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#define GITS_BASER_INDIRECT (1ULL << 62)
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#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
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#define GITS_BASER_INNER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
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#define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
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#define GITS_BASER_OUTER_CACHEABILITY_MASK \
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GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
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#define GITS_BASER_SHAREABILITY_MASK \
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GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
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#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
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#define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
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#define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
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#define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
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#define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
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#define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
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#define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
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#define GITS_BASER_TYPE_SHIFT (56)
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#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
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#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
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#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
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#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
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#define GITS_BASER_SHAREABILITY_SHIFT (10)
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#define GITS_BASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
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#define GITS_BASER_PAGE_SIZE_SHIFT (8)
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#define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
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#define GITS_BASER_PAGES_MAX 256
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#define GITS_BASER_PAGES_SHIFT (0)
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#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
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#define GITS_BASER_TYPE_NONE 0
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#define GITS_BASER_TYPE_DEVICE 1
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#define GITS_BASER_TYPE_VCPU 2
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#define GITS_BASER_TYPE_RESERVED3 3
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#define GITS_BASER_TYPE_COLLECTION 4
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#define GITS_BASER_TYPE_RESERVED5 5
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#define GITS_BASER_TYPE_RESERVED6 6
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#define GITS_BASER_TYPE_RESERVED7 7
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#define GITS_LVL1_ENTRY_SIZE (8UL)
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/*
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* ITS commands
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*/
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#define GITS_CMD_MAPD 0x08
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#define GITS_CMD_MAPC 0x09
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#define GITS_CMD_MAPTI 0x0a
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#define GITS_CMD_MAPI 0x0b
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#define GITS_CMD_MOVI 0x01
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#define GITS_CMD_DISCARD 0x0f
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#define GITS_CMD_INV 0x0c
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#define GITS_CMD_MOVALL 0x0e
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#define GITS_CMD_INVALL 0x0d
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#define GITS_CMD_INT 0x03
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#define GITS_CMD_CLEAR 0x04
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#define GITS_CMD_SYNC 0x05
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/*
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* ITS error numbers
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*/
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#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
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#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
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#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
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#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
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#define E_ITS_MAPD_DEVICE_OOR 0x010801
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#define E_ITS_MAPD_ITTSIZE_OOR 0x010802
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#define E_ITS_MAPC_PROCNUM_OOR 0x010902
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#define E_ITS_MAPC_COLLECTION_OOR 0x010903
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#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
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#define E_ITS_MAPTI_ID_OOR 0x010a05
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#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
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#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
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#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
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#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
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#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
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/*
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* CPU interface registers
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*/
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#define ICC_CTLR_EL1_EOImode_SHIFT (1)
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#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
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#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
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#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
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#define ICC_CTLR_EL1_CBPR_SHIFT 0
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#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
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#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
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#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
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#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
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#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
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#define ICC_CTLR_EL1_SEIS_SHIFT 14
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#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
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#define ICC_CTLR_EL1_A3V_SHIFT 15
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#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
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#define ICC_PMR_EL1_SHIFT 0
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#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
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#define ICC_BPR0_EL1_SHIFT 0
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#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
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#define ICC_BPR1_EL1_SHIFT 0
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#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
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#define ICC_IGRPEN0_EL1_SHIFT 0
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#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
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#define ICC_IGRPEN1_EL1_SHIFT 0
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#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
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#define ICC_SRE_EL1_DIB (1U << 2)
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#define ICC_SRE_EL1_DFB (1U << 1)
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#define ICC_SRE_EL1_SRE (1U << 0)
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/*
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* Hypervisor interface registers (SRE only)
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*/
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#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
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#define ICH_LR_EOI (1ULL << 41)
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#define ICH_LR_GROUP (1ULL << 60)
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#define ICH_LR_HW (1ULL << 61)
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#define ICH_LR_STATE (3ULL << 62)
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#define ICH_LR_PENDING_BIT (1ULL << 62)
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#define ICH_LR_ACTIVE_BIT (1ULL << 63)
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#define ICH_LR_PHYS_ID_SHIFT 32
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#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
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#define ICH_LR_PRIORITY_SHIFT 48
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/* These are for GICv2 emulation only */
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#define GICH_LR_VIRTUALID (0x3ffUL << 0)
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#define GICH_LR_PHYSID_CPUID_SHIFT (10)
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#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
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#define ICH_MISR_EOI (1 << 0)
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#define ICH_MISR_U (1 << 1)
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#define ICH_HCR_EN (1 << 0)
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#define ICH_HCR_UIE (1 << 1)
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#define ICH_VMCR_CBPR_SHIFT 4
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#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
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#define ICH_VMCR_EOIM_SHIFT 9
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#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
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#define ICH_VMCR_BPR1_SHIFT 18
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#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
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#define ICH_VMCR_BPR0_SHIFT 21
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#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
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#define ICH_VMCR_PMR_SHIFT 24
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#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
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#define ICH_VMCR_ENG0_SHIFT 0
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#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
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#define ICH_VMCR_ENG1_SHIFT 1
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#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
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#define ICH_VTR_PRI_BITS_SHIFT 29
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#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
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#define ICH_VTR_ID_BITS_SHIFT 23
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#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
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#define ICH_VTR_SEIS_SHIFT 22
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#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
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#define ICH_VTR_A3V_SHIFT 21
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#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
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#define ICC_IAR1_EL1_SPURIOUS 0x3ff
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#define ICC_SRE_EL2_SRE (1 << 0)
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#define ICC_SRE_EL2_ENABLE (1 << 3)
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#define ICC_SGI1R_TARGET_LIST_SHIFT 0
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#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
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#define ICC_SGI1R_AFFINITY_1_SHIFT 16
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#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
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#define ICC_SGI1R_SGI_ID_SHIFT 24
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#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
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#define ICC_SGI1R_AFFINITY_2_SHIFT 32
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#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
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#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
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#define ICC_SGI1R_AFFINITY_3_SHIFT 48
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#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
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#include <asm/arch_gicv3.h>
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|
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#ifndef __ASSEMBLY__
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/*
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* We need a value to serve as a irq-type for LPIs. Choose one that will
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* hopefully pique the interest of the reviewer.
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*/
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#define GIC_IRQ_TYPE_LPI 0xa110c8ed
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struct rdists {
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struct {
|
|
void __iomem *rd_base;
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struct page *pend_page;
|
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phys_addr_t phys_base;
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} __percpu *rdist;
|
|
struct page *prop_page;
|
|
int id_bits;
|
|
u64 flags;
|
|
};
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struct irq_domain;
|
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struct fwnode_handle;
|
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int its_cpu_init(void);
|
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int its_init(struct fwnode_handle *handle, struct rdists *rdists,
|
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struct irq_domain *domain);
|
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|
|
static inline bool gic_enable_sre(void)
|
|
{
|
|
u32 val;
|
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|
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val = gic_read_sre();
|
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if (val & ICC_SRE_EL1_SRE)
|
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return true;
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|
|
val |= ICC_SRE_EL1_SRE;
|
|
gic_write_sre(val);
|
|
val = gic_read_sre();
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|
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return !!(val & ICC_SRE_EL1_SRE);
|
|
}
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#endif
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#endif
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