140 lines
4.1 KiB
C
140 lines
4.1 KiB
C
#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/mips-boards/piix4.h>
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/* PCI interrupt pins */
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#define PCIA 1
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#define PCIB 2
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#define PCIC 3
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#define PCID 4
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/* This table is filled in by interrogating the PIIX4 chip */
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static char pci_irq[5] = {
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};
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static char irq_tab[][5] __initdata = {
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/* INTA INTB INTC INTD */
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{0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
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{0, 0, 0, 0, 0 }, /* 1: Unused */
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{0, 0, 0, 0, 0 }, /* 2: Unused */
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{0, 0, 0, 0, 0 }, /* 3: Unused */
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{0, 0, 0, 0, 0 }, /* 4: Unused */
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{0, 0, 0, 0, 0 }, /* 5: Unused */
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{0, 0, 0, 0, 0 }, /* 6: Unused */
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{0, 0, 0, 0, 0 }, /* 7: Unused */
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{0, 0, 0, 0, 0 }, /* 8: Unused */
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{0, 0, 0, 0, 0 }, /* 9: Unused */
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{0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
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{0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
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{0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
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{0, 0, 0, 0, 0 }, /* 13: Unused */
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{0, 0, 0, 0, 0 }, /* 14: Unused */
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{0, 0, 0, 0, 0 }, /* 15: Unused */
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{0, 0, 0, 0, 0 }, /* 16: Unused */
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{0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
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{0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
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{0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
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{0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
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{0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int virq;
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virq = irq_tab[slot][pin];
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return pci_irq[virq];
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static void malta_piix_func0_fixup(struct pci_dev *pdev)
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{
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unsigned char reg_val;
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u32 reg_val32;
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/* PIIX PIRQC[A:D] irq mappings */
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static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
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0, 0, 0, 3,
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4, 5, 6, 7,
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0, 9, 10, 11,
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12, 0, 14, 15
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};
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int i;
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/* Interrogate PIIX4 to get PCI IRQ mapping */
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for (i = 0; i <= 3; i++) {
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pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val);
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if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
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pci_irq[PCIA+i] = 0; /* Disabled */
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else
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pci_irq[PCIA+i] = piixirqmap[reg_val &
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PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
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}
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/* Done by YAMON 2.00 onwards */
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if (PCI_SLOT(pdev->devfn) == 10) {
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/*
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* Set top of main memory accessible by ISA or DMA
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* devices to 16 Mb.
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*/
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pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val);
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pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
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PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
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}
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/* Mux SERIRQ to its pin */
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pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, ®_val32);
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pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
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reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
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/* Enable SERIRQ */
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pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val);
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reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
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pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
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malta_piix_func0_fixup);
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static void malta_piix_func1_fixup(struct pci_dev *pdev)
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{
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unsigned char reg_val;
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/* Done by YAMON 2.02 onwards */
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if (PCI_SLOT(pdev->devfn) == 10) {
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/*
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* IDE Decode enable.
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*/
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pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
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®_val);
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pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
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reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
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pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
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®_val);
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pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
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reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
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malta_piix_func1_fixup);
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/* Enable PCI 2.1 compatibility in PIIX4 */
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static void quirk_dlcsetup(struct pci_dev *dev)
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{
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u8 odlc, ndlc;
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(void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
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/* Enable passive releases and delayed transaction */
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ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
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PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
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PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
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(void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
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quirk_dlcsetup);
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