318 lines
9.1 KiB
C
318 lines
9.1 KiB
C
/*
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* Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/pci-bridge.h>
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#include <asm/open_pic.h>
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#include <asm/hawk.h>
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/*
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* The Falcon/Raven and HAWK has 4 sets of registers:
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* 1) PPC Registers which define the mappings from PPC bus to PCI bus,
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* etc.
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* 2) PCI Registers which define the mappings from PCI bus to PPC bus and the
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* MPIC base address.
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* 3) MPIC registers.
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* 4) System Memory Controller (SMC) registers.
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*/
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/*
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* Initialize the Motorola MCG Raven or HAWK host bridge.
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*
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* This means setting up the PPC bus to PCI memory and I/O space mappings,
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* setting the PCI memory space address of the MPIC (mapped straight
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* through), and ioremap'ing the mpic registers.
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* This routine will set the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
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* addresses based on the PCI I/O address that is passed in.
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* 'OpenPIC_Addr' will be set correctly by this routine.
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*/
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int __init
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hawk_init(struct pci_controller *hose,
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uint ppc_reg_base,
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ulong processor_pci_mem_start,
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ulong processor_pci_mem_end,
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ulong processor_pci_io_start,
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ulong processor_pci_io_end,
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ulong processor_mpic_base)
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{
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uint addr, offset;
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/*
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* Some sanity checks...
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*/
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if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
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((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
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printk("hawk_init: %s\n",
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"PPC to PCI mappings must start on 64 KB boundaries");
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return -1;
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}
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if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) ||
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((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) {
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printk("hawk_init: PPC to PCI mappings %s\n",
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"must end just before a 64 KB boundaries");
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return -1;
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}
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if (((processor_pci_mem_end - processor_pci_mem_start) !=
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(hose->mem_space.end - hose->mem_space.start)) ||
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((processor_pci_io_end - processor_pci_io_start) !=
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(hose->io_space.end - hose->io_space.start))) {
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printk("hawk_init: %s\n",
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"PPC and PCI memory or I/O space sizes don't match");
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return -1;
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}
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if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
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printk("hawk_init: %s\n",
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"MPIC address must start on 256 MB boundary");
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return -1;
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}
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if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
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printk("hawk_init: %s\n",
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"pci_dram_offset must be multiple of 64 KB");
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return -1;
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}
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/*
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* Disable previous PPC->PCI mappings.
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*/
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
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/*
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* Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
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* space mappings. These are the mappings going from the processor to
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* the PCI bus.
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*
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* Note: Don't need to 'AND' start/end addresses with 0xffff0000
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* because sanity check above ensures that they are properly
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* aligned.
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*/
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/* Set up PPC->PCI Mem mapping */
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addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
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offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
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/* Set up PPC->MPIC mapping on the bridge */
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addr = processor_mpic_base |
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(((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
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/* No write posting for this PCI Mem space */
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offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
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/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
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addr = processor_pci_io_start | (processor_pci_io_end >> 16);
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offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
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out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
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hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
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(processor_pci_io_end - processor_pci_io_start + 1));
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/*
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* Set up the indirect method of accessing PCI config space.
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* The PCI config addr/data pair based on start addr of PCI I/O space.
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*/
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setup_indirect_pci(hose,
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processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
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processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
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/*
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* Disable previous PCI->PPC mappings.
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*/
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/* XXXX Put in mappings from PCI bus to processor bus XXXX */
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/*
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* Disable MPIC response to PCI I/O space (BAR 0).
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* Make MPIC respond to PCI Mem space at specified address.
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* (BAR 1).
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*/
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early_write_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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PCI_BASE_ADDRESS_0,
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0x00000000 | 0x1);
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early_write_config_dword(hose,
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0,
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PCI_DEVFN(0,0),
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PCI_BASE_ADDRESS_1,
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(processor_mpic_base -
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processor_pci_mem_start +
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hose->mem_space.start) | 0x0);
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/* Map MPIC into virtual memory */
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OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
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return 0;
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}
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/*
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* Find the amount of RAM present.
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* This assumes that PPCBug has initialized the memory controller (SMC)
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* on the Falcon/HAWK correctly (i.e., it does no sanity checking).
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* It also assumes that the memory base registers are set to configure the
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* memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
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* however, RAM base registers can be skipped (e.g. A, B, C are set,
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* D is skipped but E is set is okay).
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*/
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#define MB (1024*1024)
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static uint reg_offset_table[] __initdata = {
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HAWK_SMC_RAM_A_SIZE_REG_OFF,
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HAWK_SMC_RAM_B_SIZE_REG_OFF,
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HAWK_SMC_RAM_C_SIZE_REG_OFF,
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HAWK_SMC_RAM_D_SIZE_REG_OFF,
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HAWK_SMC_RAM_E_SIZE_REG_OFF,
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HAWK_SMC_RAM_F_SIZE_REG_OFF,
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HAWK_SMC_RAM_G_SIZE_REG_OFF,
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HAWK_SMC_RAM_H_SIZE_REG_OFF
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};
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static uint falcon_size_table[] __initdata = {
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0 * MB, /* 0 ==> 0 MB */
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16 * MB, /* 1 ==> 16 MB */
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32 * MB, /* 2 ==> 32 MB */
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64 * MB, /* 3 ==> 64 MB */
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128 * MB, /* 4 ==> 128 MB */
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256 * MB, /* 5 ==> 256 MB */
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1024 * MB, /* 6 ==> 1024 MB (1 GB) */
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};
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static uint hawk_size_table[] __initdata = {
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0 * MB, /* 0 ==> 0 MB */
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32 * MB, /* 1 ==> 32 MB */
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64 * MB, /* 2 ==> 64 MB */
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64 * MB, /* 3 ==> 64 MB */
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128 * MB, /* 4 ==> 128 MB */
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128 * MB, /* 5 ==> 128 MB */
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128 * MB, /* 6 ==> 128 MB */
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256 * MB, /* 7 ==> 256 MB */
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256 * MB, /* 8 ==> 256 MB */
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512 * MB, /* 9 ==> 512 MB */
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};
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/*
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* *** WARNING: You MUST have a BAT set up to map in the SMC regs ***
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*
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* Read the memory controller's registers to determine the amount of system
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* memory. Assumes that the memory controller registers are already mapped
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* into virtual memory--too early to use ioremap().
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*/
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unsigned long __init
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hawk_get_mem_size(uint smc_base)
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{
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unsigned long total;
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int i, size_table_entries, reg_limit;
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uint vend_dev_id;
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uint *size_table;
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u_char val;
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vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID);
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if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
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printk("hawk_get_mem_size: %s (0x%x)\n",
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"Not a Motorola Memory Controller", vend_dev_id);
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return 0;
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}
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vend_dev_id &= 0x0000ffff;
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if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_FALCON) {
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size_table = falcon_size_table;
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size_table_entries = sizeof(falcon_size_table) /
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sizeof(falcon_size_table[0]);
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reg_limit = FALCON_SMC_REG_COUNT;
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}
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else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
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size_table = hawk_size_table;
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size_table_entries = sizeof(hawk_size_table) /
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sizeof(hawk_size_table[0]);
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reg_limit = HAWK_SMC_REG_COUNT;
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}
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else {
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printk("hawk_get_mem_size: %s (0x%x)\n",
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"Not a Falcon or HAWK", vend_dev_id);
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return 0;
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}
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total = 0;
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/* Check every reg because PPCBug may skip some */
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for (i=0; i<reg_limit; i++) {
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val = in_8((u_char *)(smc_base + reg_offset_table[i]));
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if (val & 0x80) { /* If enabled */
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val &= 0x0f;
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/* Don't go past end of size_table */
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if (val < size_table_entries) {
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total += size_table[val];
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}
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else { /* Register not set correctly */
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break;
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}
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}
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}
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return total;
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}
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int __init
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hawk_mpic_init(unsigned int pci_mem_offset)
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{
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unsigned short devid;
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unsigned int pci_membase;
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/* Check the first PCI device to see if it is a Raven or Hawk. */
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early_read_config_word(0, 0, 0, PCI_DEVICE_ID, &devid);
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switch (devid) {
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case PCI_DEVICE_ID_MOTOROLA_RAVEN:
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case PCI_DEVICE_ID_MOTOROLA_HAWK:
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break;
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default:
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OpenPIC_Addr = NULL;
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return 1;
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}
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/* Read the memory base register. */
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early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
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if (pci_membase == 0) {
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OpenPIC_Addr = NULL;
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return 1;
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}
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/* Map the MPIC registers to virtual memory. */
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OpenPIC_Addr = ioremap(pci_membase + pci_mem_offset, 0x22000);
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return 0;
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}
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