1704 lines
44 KiB
C
1704 lines
44 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <drm/drm_print.h>
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#include "gem/i915_gem_context.h"
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#include "i915_drv.h"
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#include "intel_context.h"
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#include "intel_engine.h"
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#include "intel_engine_pm.h"
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#include "intel_engine_pool.h"
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#include "intel_engine_user.h"
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#include "intel_gt.h"
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#include "intel_gt_requests.h"
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#include "intel_lrc.h"
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#include "intel_reset.h"
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#include "intel_ring.h"
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/* Haswell does have the CXT_SIZE register however it does not appear to be
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* valid. Now, docs explain in dwords what is in the context object. The full
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* size is 70720 bytes, however, the power context and execlist context will
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* never be saved (power context is stored elsewhere, and execlists don't work
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* on HSW) - so the final size, including the extra state required for the
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* Resource Streamer, is 66944 bytes, which rounds to 17 pages.
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*/
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#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
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#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
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#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
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#define MAX_MMIO_BASES 3
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struct engine_info {
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unsigned int hw_id;
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u8 class;
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u8 instance;
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/* mmio bases table *must* be sorted in reverse gen order */
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struct engine_mmio_base {
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u32 gen : 8;
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u32 base : 24;
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} mmio_bases[MAX_MMIO_BASES];
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};
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static const struct engine_info intel_engines[] = {
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[RCS0] = {
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.hw_id = RCS0_HW,
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.class = RENDER_CLASS,
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.instance = 0,
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.mmio_bases = {
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{ .gen = 1, .base = RENDER_RING_BASE }
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},
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},
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[BCS0] = {
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.hw_id = BCS0_HW,
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.class = COPY_ENGINE_CLASS,
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.instance = 0,
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.mmio_bases = {
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{ .gen = 6, .base = BLT_RING_BASE }
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},
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},
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[VCS0] = {
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.hw_id = VCS0_HW,
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.class = VIDEO_DECODE_CLASS,
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.instance = 0,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD_RING_BASE },
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{ .gen = 6, .base = GEN6_BSD_RING_BASE },
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{ .gen = 4, .base = BSD_RING_BASE }
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},
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},
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[VCS1] = {
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.hw_id = VCS1_HW,
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.class = VIDEO_DECODE_CLASS,
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.instance = 1,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD2_RING_BASE },
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{ .gen = 8, .base = GEN8_BSD2_RING_BASE }
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},
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},
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[VCS2] = {
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.hw_id = VCS2_HW,
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.class = VIDEO_DECODE_CLASS,
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.instance = 2,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD3_RING_BASE }
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},
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},
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[VCS3] = {
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.hw_id = VCS3_HW,
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.class = VIDEO_DECODE_CLASS,
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.instance = 3,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_BSD4_RING_BASE }
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},
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},
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[VECS0] = {
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.hw_id = VECS0_HW,
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.class = VIDEO_ENHANCEMENT_CLASS,
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.instance = 0,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_VEBOX_RING_BASE },
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{ .gen = 7, .base = VEBOX_RING_BASE }
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},
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},
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[VECS1] = {
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.hw_id = VECS1_HW,
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.class = VIDEO_ENHANCEMENT_CLASS,
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.instance = 1,
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.mmio_bases = {
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{ .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
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},
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},
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};
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/**
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* intel_engine_context_size() - return the size of the context for an engine
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* @gt: the gt
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* @class: engine class
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*
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* Each engine class may require a different amount of space for a context
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* image.
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*
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* Return: size (in bytes) of an engine class specific context image
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*
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* Note: this size includes the HWSP, which is part of the context image
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* in LRC mode, but does not include the "shared data page" used with
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* GuC submission. The caller should account for this if using the GuC.
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*/
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u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
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{
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struct intel_uncore *uncore = gt->uncore;
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u32 cxt_size;
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BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
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switch (class) {
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case RENDER_CLASS:
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switch (INTEL_GEN(gt->i915)) {
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default:
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MISSING_CASE(INTEL_GEN(gt->i915));
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return DEFAULT_LR_CONTEXT_RENDER_SIZE;
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case 12:
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case 11:
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return GEN11_LR_CONTEXT_RENDER_SIZE;
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case 10:
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return GEN10_LR_CONTEXT_RENDER_SIZE;
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case 9:
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return GEN9_LR_CONTEXT_RENDER_SIZE;
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case 8:
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return GEN8_LR_CONTEXT_RENDER_SIZE;
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case 7:
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if (IS_HASWELL(gt->i915))
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return HSW_CXT_TOTAL_SIZE;
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cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
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return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 6:
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cxt_size = intel_uncore_read(uncore, CXT_SIZE);
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return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
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PAGE_SIZE);
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case 5:
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case 4:
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/*
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* There is a discrepancy here between the size reported
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* by the register and the size of the context layout
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* in the docs. Both are described as authorative!
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*
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* The discrepancy is on the order of a few cachelines,
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* but the total is under one page (4k), which is our
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* minimum allocation anyway so it should all come
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* out in the wash.
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*/
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cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
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DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
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INTEL_GEN(gt->i915),
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cxt_size * 64,
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cxt_size - 1);
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return round_up(cxt_size * 64, PAGE_SIZE);
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case 3:
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case 2:
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/* For the special day when i810 gets merged. */
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case 1:
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return 0;
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}
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break;
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default:
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MISSING_CASE(class);
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/* fall through */
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case VIDEO_DECODE_CLASS:
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case VIDEO_ENHANCEMENT_CLASS:
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case COPY_ENGINE_CLASS:
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if (INTEL_GEN(gt->i915) < 8)
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return 0;
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return GEN8_LR_CONTEXT_OTHER_SIZE;
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}
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}
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static u32 __engine_mmio_base(struct drm_i915_private *i915,
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const struct engine_mmio_base *bases)
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{
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int i;
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for (i = 0; i < MAX_MMIO_BASES; i++)
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if (INTEL_GEN(i915) >= bases[i].gen)
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break;
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GEM_BUG_ON(i == MAX_MMIO_BASES);
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GEM_BUG_ON(!bases[i].base);
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return bases[i].base;
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}
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static void __sprint_engine_name(struct intel_engine_cs *engine)
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{
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/*
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* Before we know what the uABI name for this engine will be,
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* we still would like to keep track of this engine in the debug logs.
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* We throw in a ' here as a reminder that this isn't its final name.
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*/
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GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
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intel_engine_class_repr(engine->class),
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engine->instance) >= sizeof(engine->name));
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}
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void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
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{
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/*
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* Though they added more rings on g4x/ilk, they did not add
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* per-engine HWSTAM until gen6.
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*/
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if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
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return;
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if (INTEL_GEN(engine->i915) >= 3)
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ENGINE_WRITE(engine, RING_HWSTAM, mask);
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else
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ENGINE_WRITE16(engine, RING_HWSTAM, mask);
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}
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static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
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{
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/* Mask off all writes into the unknown HWSP */
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intel_engine_set_hwsp_writemask(engine, ~0u);
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}
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static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
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{
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const struct engine_info *info = &intel_engines[id];
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struct intel_engine_cs *engine;
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BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
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BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
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if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
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return -EINVAL;
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if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
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return -EINVAL;
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if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
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return -EINVAL;
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if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
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return -EINVAL;
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engine = kzalloc(sizeof(*engine), GFP_KERNEL);
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if (!engine)
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return -ENOMEM;
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BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
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engine->id = id;
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engine->legacy_idx = INVALID_ENGINE;
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engine->mask = BIT(id);
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engine->i915 = gt->i915;
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engine->gt = gt;
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engine->uncore = gt->uncore;
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engine->hw_id = engine->guc_id = info->hw_id;
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engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases);
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engine->class = info->class;
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engine->instance = info->instance;
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__sprint_engine_name(engine);
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engine->props.heartbeat_interval_ms =
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CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
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engine->props.preempt_timeout_ms =
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CONFIG_DRM_I915_PREEMPT_TIMEOUT;
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engine->props.stop_timeout_ms =
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CONFIG_DRM_I915_STOP_TIMEOUT;
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engine->props.timeslice_duration_ms =
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CONFIG_DRM_I915_TIMESLICE_DURATION;
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/*
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* To be overridden by the backend on setup. However to facilitate
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* cleanup on error during setup, we always provide the destroy vfunc.
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*/
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engine->destroy = (typeof(engine->destroy))kfree;
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engine->context_size = intel_engine_context_size(gt, engine->class);
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if (WARN_ON(engine->context_size > BIT(20)))
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engine->context_size = 0;
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if (engine->context_size)
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DRIVER_CAPS(gt->i915)->has_logical_contexts = true;
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/* Nothing to do here, execute in order of dependencies */
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engine->schedule = NULL;
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seqlock_init(&engine->stats.lock);
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ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
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/* Scrub mmio state on takeover */
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intel_engine_sanitize_mmio(engine);
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gt->engine_class[info->class][info->instance] = engine;
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gt->engine[id] = engine;
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gt->i915->engine[id] = engine;
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return 0;
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}
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static void __setup_engine_capabilities(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *i915 = engine->i915;
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if (engine->class == VIDEO_DECODE_CLASS) {
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/*
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* HEVC support is present on first engine instance
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* before Gen11 and on all instances afterwards.
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*/
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if (INTEL_GEN(i915) >= 11 ||
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(INTEL_GEN(i915) >= 9 && engine->instance == 0))
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engine->uabi_capabilities |=
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I915_VIDEO_CLASS_CAPABILITY_HEVC;
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/*
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* SFC block is present only on even logical engine
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* instances.
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*/
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if ((INTEL_GEN(i915) >= 11 &&
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RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
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(INTEL_GEN(i915) >= 9 && engine->instance == 0))
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engine->uabi_capabilities |=
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I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
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} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
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if (INTEL_GEN(i915) >= 9)
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engine->uabi_capabilities |=
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I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
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}
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}
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static void intel_setup_engine_capabilities(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, gt, id)
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__setup_engine_capabilities(engine);
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}
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/**
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* intel_engines_cleanup() - free the resources allocated for Command Streamers
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* @gt: pointer to struct intel_gt
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*/
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void intel_engines_cleanup(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, gt, id) {
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engine->destroy(engine);
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gt->engine[id] = NULL;
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gt->i915->engine[id] = NULL;
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}
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}
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/**
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* intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
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* @gt: pointer to struct intel_gt
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*
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* Return: non-zero if the initialization failed.
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*/
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int intel_engines_init_mmio(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_device_info *device_info = mkwrite_device_info(i915);
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const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
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unsigned int mask = 0;
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unsigned int i;
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int err;
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WARN_ON(engine_mask == 0);
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WARN_ON(engine_mask &
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GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
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if (i915_inject_probe_failure(i915))
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
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if (!HAS_ENGINE(i915, i))
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continue;
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err = intel_engine_setup(gt, i);
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if (err)
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goto cleanup;
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mask |= BIT(i);
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}
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|
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/*
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* Catch failures to update intel_engines table when the new engines
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* are added to the driver by a warning and disabling the forgotten
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* engines.
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*/
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if (WARN_ON(mask != engine_mask))
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device_info->engine_mask = mask;
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RUNTIME_INFO(i915)->num_engines = hweight32(mask);
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intel_gt_check_and_clear_faults(gt);
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intel_setup_engine_capabilities(gt);
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return 0;
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cleanup:
|
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intel_engines_cleanup(gt);
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return err;
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}
|
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|
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/**
|
|
* intel_engines_init() - init the Engine Command Streamers
|
|
* @gt: pointer to struct intel_gt
|
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*
|
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* Return: non-zero if the initialization failed.
|
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*/
|
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int intel_engines_init(struct intel_gt *gt)
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{
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int (*init)(struct intel_engine_cs *engine);
|
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int err;
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|
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if (HAS_EXECLISTS(gt->i915))
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init = intel_execlists_submission_init;
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else
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init = intel_ring_submission_init;
|
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|
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for_each_engine(engine, gt, id) {
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err = init(engine);
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if (err)
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goto cleanup;
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|
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intel_engine_add_user(engine);
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}
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|
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return 0;
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|
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cleanup:
|
|
intel_engines_cleanup(gt);
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return err;
|
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}
|
|
|
|
void intel_engine_init_execlists(struct intel_engine_cs *engine)
|
|
{
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|
struct intel_engine_execlists * const execlists = &engine->execlists;
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|
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execlists->port_mask = 1;
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GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
|
|
GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
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|
|
|
memset(execlists->pending, 0, sizeof(execlists->pending));
|
|
execlists->active =
|
|
memset(execlists->inflight, 0, sizeof(execlists->inflight));
|
|
|
|
execlists->queue_priority_hint = INT_MIN;
|
|
execlists->queue = RB_ROOT_CACHED;
|
|
}
|
|
|
|
static void cleanup_status_page(struct intel_engine_cs *engine)
|
|
{
|
|
struct i915_vma *vma;
|
|
|
|
/* Prevent writes into HWSP after returning the page to the system */
|
|
intel_engine_set_hwsp_writemask(engine, ~0u);
|
|
|
|
vma = fetch_and_zero(&engine->status_page.vma);
|
|
if (!vma)
|
|
return;
|
|
|
|
if (!HWS_NEEDS_PHYSICAL(engine->i915))
|
|
i915_vma_unpin(vma);
|
|
|
|
i915_gem_object_unpin_map(vma->obj);
|
|
i915_gem_object_put(vma->obj);
|
|
}
|
|
|
|
static int pin_ggtt_status_page(struct intel_engine_cs *engine,
|
|
struct i915_vma *vma)
|
|
{
|
|
unsigned int flags;
|
|
|
|
flags = PIN_GLOBAL;
|
|
if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
|
|
/*
|
|
* On g33, we cannot place HWS above 256MiB, so
|
|
* restrict its pinning to the low mappable arena.
|
|
* Though this restriction is not documented for
|
|
* gen4, gen5, or byt, they also behave similarly
|
|
* and hang if the HWS is placed at the top of the
|
|
* GTT. To generalise, it appears that all !llc
|
|
* platforms have issues with us placing the HWS
|
|
* above the mappable region (even though we never
|
|
* actually map it).
|
|
*/
|
|
flags |= PIN_MAPPABLE;
|
|
else
|
|
flags |= PIN_HIGH;
|
|
|
|
return i915_vma_pin(vma, 0, 0, flags);
|
|
}
|
|
|
|
static int init_status_page(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_gem_object *obj;
|
|
struct i915_vma *vma;
|
|
void *vaddr;
|
|
int ret;
|
|
|
|
/*
|
|
* Though the HWS register does support 36bit addresses, historically
|
|
* we have had hangs and corruption reported due to wild writes if
|
|
* the HWS is placed above 4G. We only allow objects to be allocated
|
|
* in GFP_DMA32 for i965, and no earlier physical address users had
|
|
* access to more than 4G.
|
|
*/
|
|
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
|
|
if (IS_ERR(obj)) {
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
return PTR_ERR(obj);
|
|
}
|
|
|
|
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
|
|
|
|
vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
|
|
if (IS_ERR(vma)) {
|
|
ret = PTR_ERR(vma);
|
|
goto err;
|
|
}
|
|
|
|
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
|
|
if (IS_ERR(vaddr)) {
|
|
ret = PTR_ERR(vaddr);
|
|
goto err;
|
|
}
|
|
|
|
engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
|
|
engine->status_page.vma = vma;
|
|
|
|
if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
|
|
ret = pin_ggtt_status_page(engine, vma);
|
|
if (ret)
|
|
goto err_unpin;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_unpin:
|
|
i915_gem_object_unpin_map(obj);
|
|
err:
|
|
i915_gem_object_put(obj);
|
|
return ret;
|
|
}
|
|
|
|
static int intel_engine_setup_common(struct intel_engine_cs *engine)
|
|
{
|
|
int err;
|
|
|
|
init_llist_head(&engine->barrier_tasks);
|
|
|
|
err = init_status_page(engine);
|
|
if (err)
|
|
return err;
|
|
|
|
intel_engine_init_active(engine, ENGINE_PHYSICAL);
|
|
intel_engine_init_breadcrumbs(engine);
|
|
intel_engine_init_execlists(engine);
|
|
intel_engine_init_cmd_parser(engine);
|
|
intel_engine_init__pm(engine);
|
|
intel_engine_init_retire(engine);
|
|
|
|
intel_engine_pool_init(&engine->pool);
|
|
|
|
/* Use the whole device by default */
|
|
engine->sseu =
|
|
intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
|
|
|
|
intel_engine_init_workarounds(engine);
|
|
intel_engine_init_whitelist(engine);
|
|
intel_engine_init_ctx_wa(engine);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_engines_setup- setup engine state not requiring hw access
|
|
* @gt: pointer to struct intel_gt
|
|
*
|
|
* Initializes engine structure members shared between legacy and execlists
|
|
* submission modes which do not require hardware access.
|
|
*
|
|
* Typically done early in the submission mode specific engine setup stage.
|
|
*/
|
|
int intel_engines_setup(struct intel_gt *gt)
|
|
{
|
|
int (*setup)(struct intel_engine_cs *engine);
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
int err;
|
|
|
|
if (HAS_EXECLISTS(gt->i915))
|
|
setup = intel_execlists_submission_setup;
|
|
else
|
|
setup = intel_ring_submission_setup;
|
|
|
|
for_each_engine(engine, gt, id) {
|
|
err = intel_engine_setup_common(engine);
|
|
if (err)
|
|
goto cleanup;
|
|
|
|
err = setup(engine);
|
|
if (err)
|
|
goto cleanup;
|
|
|
|
/* We expect the backend to take control over its state */
|
|
GEM_BUG_ON(engine->destroy == (typeof(engine->destroy))kfree);
|
|
|
|
GEM_BUG_ON(!engine->cops);
|
|
}
|
|
|
|
return 0;
|
|
|
|
cleanup:
|
|
intel_engines_cleanup(gt);
|
|
return err;
|
|
}
|
|
|
|
struct measure_breadcrumb {
|
|
struct i915_request rq;
|
|
struct intel_timeline timeline;
|
|
struct intel_ring ring;
|
|
u32 cs[1024];
|
|
};
|
|
|
|
static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
|
|
{
|
|
struct measure_breadcrumb *frame;
|
|
int dw = -ENOMEM;
|
|
|
|
GEM_BUG_ON(!engine->gt->scratch);
|
|
|
|
frame = kzalloc(sizeof(*frame), GFP_KERNEL);
|
|
if (!frame)
|
|
return -ENOMEM;
|
|
|
|
if (intel_timeline_init(&frame->timeline,
|
|
engine->gt,
|
|
engine->status_page.vma))
|
|
goto out_frame;
|
|
|
|
mutex_lock(&frame->timeline.mutex);
|
|
|
|
frame->ring.vaddr = frame->cs;
|
|
frame->ring.size = sizeof(frame->cs);
|
|
frame->ring.effective_size = frame->ring.size;
|
|
intel_ring_update_space(&frame->ring);
|
|
|
|
frame->rq.i915 = engine->i915;
|
|
frame->rq.engine = engine;
|
|
frame->rq.ring = &frame->ring;
|
|
rcu_assign_pointer(frame->rq.timeline, &frame->timeline);
|
|
|
|
dw = intel_timeline_pin(&frame->timeline);
|
|
if (dw < 0)
|
|
goto out_timeline;
|
|
|
|
spin_lock_irq(&engine->active.lock);
|
|
dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
|
|
spin_unlock_irq(&engine->active.lock);
|
|
|
|
GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
|
|
|
|
intel_timeline_unpin(&frame->timeline);
|
|
|
|
out_timeline:
|
|
mutex_unlock(&frame->timeline.mutex);
|
|
intel_timeline_fini(&frame->timeline);
|
|
out_frame:
|
|
kfree(frame);
|
|
return dw;
|
|
}
|
|
|
|
void
|
|
intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
|
|
{
|
|
INIT_LIST_HEAD(&engine->active.requests);
|
|
|
|
spin_lock_init(&engine->active.lock);
|
|
lockdep_set_subclass(&engine->active.lock, subclass);
|
|
|
|
/*
|
|
* Due to an interesting quirk in lockdep's internal debug tracking,
|
|
* after setting a subclass we must ensure the lock is used. Otherwise,
|
|
* nr_unused_locks is incremented once too often.
|
|
*/
|
|
#ifdef CONFIG_DEBUG_LOCK_ALLOC
|
|
local_irq_disable();
|
|
lock_map_acquire(&engine->active.lock.dep_map);
|
|
lock_map_release(&engine->active.lock.dep_map);
|
|
local_irq_enable();
|
|
#endif
|
|
}
|
|
|
|
static struct intel_context *
|
|
create_kernel_context(struct intel_engine_cs *engine)
|
|
{
|
|
static struct lock_class_key kernel;
|
|
struct intel_context *ce;
|
|
int err;
|
|
|
|
ce = intel_context_create(engine->i915->kernel_context, engine);
|
|
if (IS_ERR(ce))
|
|
return ce;
|
|
|
|
ce->ring = __intel_context_ring_size(SZ_4K);
|
|
|
|
err = intel_context_pin(ce);
|
|
if (err) {
|
|
intel_context_put(ce);
|
|
return ERR_PTR(err);
|
|
}
|
|
|
|
/*
|
|
* Give our perma-pinned kernel timelines a separate lockdep class,
|
|
* so that we can use them from within the normal user timelines
|
|
* should we need to inject GPU operations during their request
|
|
* construction.
|
|
*/
|
|
lockdep_set_class(&ce->timeline->mutex, &kernel);
|
|
|
|
return ce;
|
|
}
|
|
|
|
/**
|
|
* intel_engines_init_common - initialize cengine state which might require hw access
|
|
* @engine: Engine to initialize.
|
|
*
|
|
* Initializes @engine@ structure members shared between legacy and execlists
|
|
* submission modes which do require hardware access.
|
|
*
|
|
* Typcally done at later stages of submission mode specific engine setup.
|
|
*
|
|
* Returns zero on success or an error code on failure.
|
|
*/
|
|
int intel_engine_init_common(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_context *ce;
|
|
int ret;
|
|
|
|
engine->set_default_submission(engine);
|
|
|
|
/*
|
|
* We may need to do things with the shrinker which
|
|
* require us to immediately switch back to the default
|
|
* context. This can cause a problem as pinning the
|
|
* default context also requires GTT space which may not
|
|
* be available. To avoid this we always pin the default
|
|
* context.
|
|
*/
|
|
ce = create_kernel_context(engine);
|
|
if (IS_ERR(ce))
|
|
return PTR_ERR(ce);
|
|
|
|
engine->kernel_context = ce;
|
|
|
|
ret = measure_breadcrumb_dw(engine);
|
|
if (ret < 0)
|
|
goto err_unpin;
|
|
|
|
engine->emit_fini_breadcrumb_dw = ret;
|
|
|
|
return 0;
|
|
|
|
err_unpin:
|
|
intel_context_unpin(ce);
|
|
intel_context_put(ce);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* intel_engines_cleanup_common - cleans up the engine state created by
|
|
* the common initiailizers.
|
|
* @engine: Engine to cleanup.
|
|
*
|
|
* This cleans up everything created by the common helpers.
|
|
*/
|
|
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
|
|
{
|
|
GEM_BUG_ON(!list_empty(&engine->active.requests));
|
|
|
|
cleanup_status_page(engine);
|
|
|
|
intel_engine_fini_retire(engine);
|
|
intel_engine_pool_fini(&engine->pool);
|
|
intel_engine_fini_breadcrumbs(engine);
|
|
intel_engine_cleanup_cmd_parser(engine);
|
|
|
|
if (engine->default_state)
|
|
i915_gem_object_put(engine->default_state);
|
|
|
|
if (engine->kernel_context) {
|
|
intel_context_unpin(engine->kernel_context);
|
|
intel_context_put(engine->kernel_context);
|
|
}
|
|
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
|
|
|
|
intel_wa_list_free(&engine->ctx_wa_list);
|
|
intel_wa_list_free(&engine->wa_list);
|
|
intel_wa_list_free(&engine->whitelist);
|
|
}
|
|
|
|
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
|
|
u64 acthd;
|
|
|
|
if (INTEL_GEN(i915) >= 8)
|
|
acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
|
|
else if (INTEL_GEN(i915) >= 4)
|
|
acthd = ENGINE_READ(engine, RING_ACTHD);
|
|
else
|
|
acthd = ENGINE_READ(engine, ACTHD);
|
|
|
|
return acthd;
|
|
}
|
|
|
|
u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
|
|
{
|
|
u64 bbaddr;
|
|
|
|
if (INTEL_GEN(engine->i915) >= 8)
|
|
bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
|
|
else
|
|
bbaddr = ENGINE_READ(engine, RING_BBADDR);
|
|
|
|
return bbaddr;
|
|
}
|
|
|
|
static unsigned long stop_timeout(const struct intel_engine_cs *engine)
|
|
{
|
|
if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
|
|
return 0;
|
|
|
|
/*
|
|
* If we are doing a normal GPU reset, we can take our time and allow
|
|
* the engine to quiesce. We've stopped submission to the engine, and
|
|
* if we wait long enough an innocent context should complete and
|
|
* leave the engine idle. So they should not be caught unaware by
|
|
* the forthcoming GPU reset (which usually follows the stop_cs)!
|
|
*/
|
|
return READ_ONCE(engine->props.stop_timeout_ms);
|
|
}
|
|
|
|
int intel_engine_stop_cs(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_uncore *uncore = engine->uncore;
|
|
const u32 base = engine->mmio_base;
|
|
const i915_reg_t mode = RING_MI_MODE(base);
|
|
int err;
|
|
|
|
if (INTEL_GEN(engine->i915) < 3)
|
|
return -ENODEV;
|
|
|
|
GEM_TRACE("%s\n", engine->name);
|
|
|
|
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
|
|
|
|
err = 0;
|
|
if (__intel_wait_for_register_fw(uncore,
|
|
mode, MODE_IDLE, MODE_IDLE,
|
|
1000, stop_timeout(engine),
|
|
NULL)) {
|
|
GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
|
|
err = -ETIMEDOUT;
|
|
}
|
|
|
|
/* A final mmio read to let GPU writes be hopefully flushed to memory */
|
|
intel_uncore_posting_read_fw(uncore, mode);
|
|
|
|
return err;
|
|
}
|
|
|
|
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
|
|
{
|
|
GEM_TRACE("%s\n", engine->name);
|
|
|
|
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
|
|
}
|
|
|
|
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
|
|
{
|
|
switch (type) {
|
|
case I915_CACHE_NONE: return " uncached";
|
|
case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
|
|
case I915_CACHE_L3_LLC: return " L3+LLC";
|
|
case I915_CACHE_WT: return " WT";
|
|
default: return "";
|
|
}
|
|
}
|
|
|
|
static u32
|
|
read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
|
|
i915_reg_t reg)
|
|
{
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
struct intel_uncore *uncore = engine->uncore;
|
|
u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
|
|
enum forcewake_domains fw_domains;
|
|
|
|
if (INTEL_GEN(i915) >= 11) {
|
|
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
|
|
mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
|
|
} else {
|
|
mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
|
|
mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
|
|
}
|
|
|
|
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
|
|
FW_REG_READ);
|
|
fw_domains |= intel_uncore_forcewake_for_reg(uncore,
|
|
GEN8_MCR_SELECTOR,
|
|
FW_REG_READ | FW_REG_WRITE);
|
|
|
|
spin_lock_irq(&uncore->lock);
|
|
intel_uncore_forcewake_get__locked(uncore, fw_domains);
|
|
|
|
old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
|
|
|
|
mcr &= ~mcr_mask;
|
|
mcr |= mcr_ss;
|
|
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
|
|
|
|
val = intel_uncore_read_fw(uncore, reg);
|
|
|
|
mcr &= ~mcr_mask;
|
|
mcr |= old_mcr & mcr_mask;
|
|
|
|
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
|
|
|
|
intel_uncore_forcewake_put__locked(uncore, fw_domains);
|
|
spin_unlock_irq(&uncore->lock);
|
|
|
|
return val;
|
|
}
|
|
|
|
/* NB: please notice the memset */
|
|
void intel_engine_get_instdone(struct intel_engine_cs *engine,
|
|
struct intel_instdone *instdone)
|
|
{
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
|
|
struct intel_uncore *uncore = engine->uncore;
|
|
u32 mmio_base = engine->mmio_base;
|
|
int slice;
|
|
int subslice;
|
|
|
|
memset(instdone, 0, sizeof(*instdone));
|
|
|
|
switch (INTEL_GEN(i915)) {
|
|
default:
|
|
instdone->instdone =
|
|
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
|
|
|
|
if (engine->id != RCS0)
|
|
break;
|
|
|
|
instdone->slice_common =
|
|
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
|
|
for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
|
|
instdone->sampler[slice][subslice] =
|
|
read_subslice_reg(engine, slice, subslice,
|
|
GEN7_SAMPLER_INSTDONE);
|
|
instdone->row[slice][subslice] =
|
|
read_subslice_reg(engine, slice, subslice,
|
|
GEN7_ROW_INSTDONE);
|
|
}
|
|
break;
|
|
case 7:
|
|
instdone->instdone =
|
|
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
|
|
|
|
if (engine->id != RCS0)
|
|
break;
|
|
|
|
instdone->slice_common =
|
|
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
|
|
instdone->sampler[0][0] =
|
|
intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
|
|
instdone->row[0][0] =
|
|
intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
|
|
|
|
break;
|
|
case 6:
|
|
case 5:
|
|
case 4:
|
|
instdone->instdone =
|
|
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
|
|
if (engine->id == RCS0)
|
|
/* HACK: Using the wrong struct member */
|
|
instdone->slice_common =
|
|
intel_uncore_read(uncore, GEN4_INSTDONE1);
|
|
break;
|
|
case 3:
|
|
case 2:
|
|
instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static bool ring_is_idle(struct intel_engine_cs *engine)
|
|
{
|
|
bool idle = true;
|
|
|
|
if (I915_SELFTEST_ONLY(!engine->mmio_base))
|
|
return true;
|
|
|
|
if (!intel_engine_pm_get_if_awake(engine))
|
|
return true;
|
|
|
|
/* First check that no commands are left in the ring */
|
|
if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
|
|
(ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
|
|
idle = false;
|
|
|
|
/* No bit for gen2, so assume the CS parser is idle */
|
|
if (INTEL_GEN(engine->i915) > 2 &&
|
|
!(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
|
|
idle = false;
|
|
|
|
intel_engine_pm_put(engine);
|
|
|
|
return idle;
|
|
}
|
|
|
|
void intel_engine_flush_submission(struct intel_engine_cs *engine)
|
|
{
|
|
struct tasklet_struct *t = &engine->execlists.tasklet;
|
|
|
|
if (__tasklet_is_scheduled(t)) {
|
|
local_bh_disable();
|
|
if (tasklet_trylock(t)) {
|
|
/* Must wait for any GPU reset in progress. */
|
|
if (__tasklet_is_enabled(t))
|
|
t->func(t->data);
|
|
tasklet_unlock(t);
|
|
}
|
|
local_bh_enable();
|
|
}
|
|
|
|
/* Otherwise flush the tasklet if it was running on another cpu */
|
|
tasklet_unlock_wait(t);
|
|
}
|
|
|
|
/**
|
|
* intel_engine_is_idle() - Report if the engine has finished process all work
|
|
* @engine: the intel_engine_cs
|
|
*
|
|
* Return true if there are no requests pending, nothing left to be submitted
|
|
* to hardware, and that the engine is idle.
|
|
*/
|
|
bool intel_engine_is_idle(struct intel_engine_cs *engine)
|
|
{
|
|
/* More white lies, if wedged, hw state is inconsistent */
|
|
if (intel_gt_is_wedged(engine->gt))
|
|
return true;
|
|
|
|
if (!intel_engine_pm_is_awake(engine))
|
|
return true;
|
|
|
|
/* Waiting to drain ELSP? */
|
|
if (execlists_active(&engine->execlists)) {
|
|
synchronize_hardirq(engine->i915->drm.pdev->irq);
|
|
|
|
intel_engine_flush_submission(engine);
|
|
|
|
if (execlists_active(&engine->execlists))
|
|
return false;
|
|
}
|
|
|
|
/* ELSP is empty, but there are ready requests? E.g. after reset */
|
|
if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
|
|
return false;
|
|
|
|
/* Ring stopped? */
|
|
return ring_is_idle(engine);
|
|
}
|
|
|
|
bool intel_engines_are_idle(struct intel_gt *gt)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
/*
|
|
* If the driver is wedged, HW state may be very inconsistent and
|
|
* report that it is still busy, even though we have stopped using it.
|
|
*/
|
|
if (intel_gt_is_wedged(gt))
|
|
return true;
|
|
|
|
/* Already parked (and passed an idleness test); must still be idle */
|
|
if (!READ_ONCE(gt->awake))
|
|
return true;
|
|
|
|
for_each_engine(engine, gt, id) {
|
|
if (!intel_engine_is_idle(engine))
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void intel_engines_reset_default_submission(struct intel_gt *gt)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
for_each_engine(engine, gt, id)
|
|
engine->set_default_submission(engine);
|
|
}
|
|
|
|
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
|
|
{
|
|
switch (INTEL_GEN(engine->i915)) {
|
|
case 2:
|
|
return false; /* uses physical not virtual addresses */
|
|
case 3:
|
|
/* maybe only uses physical not virtual addresses */
|
|
return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
|
|
case 4:
|
|
return !IS_I965G(engine->i915); /* who knows! */
|
|
case 6:
|
|
return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
static int print_sched_attr(struct drm_i915_private *i915,
|
|
const struct i915_sched_attr *attr,
|
|
char *buf, int x, int len)
|
|
{
|
|
if (attr->priority == I915_PRIORITY_INVALID)
|
|
return x;
|
|
|
|
x += snprintf(buf + x, len - x,
|
|
" prio=%d", attr->priority);
|
|
|
|
return x;
|
|
}
|
|
|
|
static void print_request(struct drm_printer *m,
|
|
struct i915_request *rq,
|
|
const char *prefix)
|
|
{
|
|
const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
|
|
char buf[80] = "";
|
|
int x = 0;
|
|
|
|
x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf));
|
|
|
|
drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
|
|
prefix,
|
|
rq->fence.context, rq->fence.seqno,
|
|
i915_request_completed(rq) ? "!" :
|
|
i915_request_started(rq) ? "*" :
|
|
"",
|
|
test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
|
|
&rq->fence.flags) ? "+" :
|
|
test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
|
|
&rq->fence.flags) ? "-" :
|
|
"",
|
|
buf,
|
|
jiffies_to_msecs(jiffies - rq->emitted_jiffies),
|
|
name);
|
|
}
|
|
|
|
static void hexdump(struct drm_printer *m, const void *buf, size_t len)
|
|
{
|
|
const size_t rowsize = 8 * sizeof(u32);
|
|
const void *prev = NULL;
|
|
bool skip = false;
|
|
size_t pos;
|
|
|
|
for (pos = 0; pos < len; pos += rowsize) {
|
|
char line[128];
|
|
|
|
if (prev && !memcmp(prev, buf + pos, rowsize)) {
|
|
if (!skip) {
|
|
drm_printf(m, "*\n");
|
|
skip = true;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
|
|
rowsize, sizeof(u32),
|
|
line, sizeof(line),
|
|
false) >= sizeof(line));
|
|
drm_printf(m, "[%04zx] %s\n", pos, line);
|
|
|
|
prev = buf + pos;
|
|
skip = false;
|
|
}
|
|
}
|
|
|
|
static struct intel_timeline *get_timeline(struct i915_request *rq)
|
|
{
|
|
struct intel_timeline *tl;
|
|
|
|
/*
|
|
* Even though we are holding the engine->active.lock here, there
|
|
* is no control over the submission queue per-se and we are
|
|
* inspecting the active state at a random point in time, with an
|
|
* unknown queue. Play safe and make sure the timeline remains valid.
|
|
* (Only being used for pretty printing, one extra kref shouldn't
|
|
* cause a camel stampede!)
|
|
*/
|
|
rcu_read_lock();
|
|
tl = rcu_dereference(rq->timeline);
|
|
if (!kref_get_unless_zero(&tl->kref))
|
|
tl = NULL;
|
|
rcu_read_unlock();
|
|
|
|
return tl;
|
|
}
|
|
|
|
static const char *repr_timer(const struct timer_list *t)
|
|
{
|
|
if (!READ_ONCE(t->expires))
|
|
return "inactive";
|
|
|
|
if (timer_pending(t))
|
|
return "active";
|
|
|
|
return "expired";
|
|
}
|
|
|
|
static void intel_engine_print_registers(struct intel_engine_cs *engine,
|
|
struct drm_printer *m)
|
|
{
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
|
struct intel_engine_execlists * const execlists = &engine->execlists;
|
|
u64 addr;
|
|
|
|
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
|
|
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
|
|
drm_printf(m, "\tRING_START: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_START));
|
|
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
|
|
drm_printf(m, "\tRING_TAIL: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
|
|
drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
|
|
ENGINE_READ(engine, RING_CTL),
|
|
ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
|
|
if (INTEL_GEN(engine->i915) > 2) {
|
|
drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
|
|
ENGINE_READ(engine, RING_MI_MODE),
|
|
ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
|
|
}
|
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
|
drm_printf(m, "\tRING_IMR: %08x\n",
|
|
ENGINE_READ(engine, RING_IMR));
|
|
}
|
|
|
|
addr = intel_engine_get_active_head(engine);
|
|
drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
|
addr = intel_engine_get_last_batch_head(engine);
|
|
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
|
addr = ENGINE_READ(engine, RING_DMA_FADD);
|
|
else
|
|
addr = ENGINE_READ(engine, DMA_FADD_I8XX);
|
|
drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
|
|
upper_32_bits(addr), lower_32_bits(addr));
|
|
if (INTEL_GEN(dev_priv) >= 4) {
|
|
drm_printf(m, "\tIPEIR: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_IPEIR));
|
|
drm_printf(m, "\tIPEHR: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_IPEHR));
|
|
} else {
|
|
drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
|
|
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
|
|
}
|
|
|
|
if (HAS_EXECLISTS(dev_priv)) {
|
|
struct i915_request * const *port, *rq;
|
|
const u32 *hws =
|
|
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
|
|
const u8 num_entries = execlists->csb_size;
|
|
unsigned int idx;
|
|
u8 read, write;
|
|
|
|
drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
|
|
yesno(test_bit(TASKLET_STATE_SCHED,
|
|
&engine->execlists.tasklet.state)),
|
|
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
|
|
repr_timer(&engine->execlists.preempt),
|
|
repr_timer(&engine->execlists.timer));
|
|
|
|
read = execlists->csb_head;
|
|
write = READ_ONCE(*execlists->csb_write);
|
|
|
|
drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
|
|
ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
|
|
ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
|
|
read, write, num_entries);
|
|
|
|
if (read >= num_entries)
|
|
read = 0;
|
|
if (write >= num_entries)
|
|
write = 0;
|
|
if (read > write)
|
|
write += num_entries;
|
|
while (read < write) {
|
|
idx = ++read % num_entries;
|
|
drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
|
|
idx, hws[idx * 2], hws[idx * 2 + 1]);
|
|
}
|
|
|
|
execlists_active_lock_bh(execlists);
|
|
rcu_read_lock();
|
|
for (port = execlists->active; (rq = *port); port++) {
|
|
char hdr[80];
|
|
int len;
|
|
|
|
len = snprintf(hdr, sizeof(hdr),
|
|
"\t\tActive[%d]: ",
|
|
(int)(port - execlists->active));
|
|
if (!i915_request_signaled(rq)) {
|
|
struct intel_timeline *tl = get_timeline(rq);
|
|
|
|
len += snprintf(hdr + len, sizeof(hdr) - len,
|
|
"ring:{start:%08x, hwsp:%08x, seqno:%08x}, ",
|
|
i915_ggtt_offset(rq->ring->vma),
|
|
tl ? tl->hwsp_offset : 0,
|
|
hwsp_seqno(rq));
|
|
|
|
if (tl)
|
|
intel_timeline_put(tl);
|
|
}
|
|
snprintf(hdr + len, sizeof(hdr) - len, "rq: ");
|
|
print_request(m, rq, hdr);
|
|
}
|
|
for (port = execlists->pending; (rq = *port); port++) {
|
|
struct intel_timeline *tl = get_timeline(rq);
|
|
char hdr[80];
|
|
|
|
snprintf(hdr, sizeof(hdr),
|
|
"\t\tPending[%d] ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",
|
|
(int)(port - execlists->pending),
|
|
i915_ggtt_offset(rq->ring->vma),
|
|
tl ? tl->hwsp_offset : 0,
|
|
hwsp_seqno(rq));
|
|
print_request(m, rq, hdr);
|
|
|
|
if (tl)
|
|
intel_timeline_put(tl);
|
|
}
|
|
rcu_read_unlock();
|
|
execlists_active_unlock_bh(execlists);
|
|
} else if (INTEL_GEN(dev_priv) > 6) {
|
|
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_PP_DIR_BASE));
|
|
drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
|
|
drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
|
|
ENGINE_READ(engine, RING_PP_DIR_DCLV));
|
|
}
|
|
}
|
|
|
|
static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
|
|
{
|
|
void *ring;
|
|
int size;
|
|
|
|
drm_printf(m,
|
|
"[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
|
|
rq->head, rq->postfix, rq->tail,
|
|
rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
|
|
rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
|
|
|
|
size = rq->tail - rq->head;
|
|
if (rq->tail < rq->head)
|
|
size += rq->ring->size;
|
|
|
|
ring = kmalloc(size, GFP_ATOMIC);
|
|
if (ring) {
|
|
const void *vaddr = rq->ring->vaddr;
|
|
unsigned int head = rq->head;
|
|
unsigned int len = 0;
|
|
|
|
if (rq->tail < head) {
|
|
len = rq->ring->size - head;
|
|
memcpy(ring, vaddr + head, len);
|
|
head = 0;
|
|
}
|
|
memcpy(ring + len, vaddr + head, size - len);
|
|
|
|
hexdump(m, ring, size);
|
|
kfree(ring);
|
|
}
|
|
}
|
|
|
|
void intel_engine_dump(struct intel_engine_cs *engine,
|
|
struct drm_printer *m,
|
|
const char *header, ...)
|
|
{
|
|
struct i915_gpu_error * const error = &engine->i915->gpu_error;
|
|
struct i915_request *rq;
|
|
intel_wakeref_t wakeref;
|
|
unsigned long flags;
|
|
|
|
if (header) {
|
|
va_list ap;
|
|
|
|
va_start(ap, header);
|
|
drm_vprintf(m, header, &ap);
|
|
va_end(ap);
|
|
}
|
|
|
|
if (intel_gt_is_wedged(engine->gt))
|
|
drm_printf(m, "*** WEDGED ***\n");
|
|
|
|
drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
|
|
drm_printf(m, "\tBarriers?: %s\n",
|
|
yesno(!llist_empty(&engine->barrier_tasks)));
|
|
|
|
rcu_read_lock();
|
|
rq = READ_ONCE(engine->heartbeat.systole);
|
|
if (rq)
|
|
drm_printf(m, "\tHeartbeat: %d ms ago\n",
|
|
jiffies_to_msecs(jiffies - rq->emitted_jiffies));
|
|
rcu_read_unlock();
|
|
drm_printf(m, "\tReset count: %d (global %d)\n",
|
|
i915_reset_engine_count(error, engine),
|
|
i915_reset_count(error));
|
|
|
|
drm_printf(m, "\tRequests:\n");
|
|
|
|
spin_lock_irqsave(&engine->active.lock, flags);
|
|
rq = intel_engine_find_active_request(engine);
|
|
if (rq) {
|
|
struct intel_timeline *tl = get_timeline(rq);
|
|
|
|
print_request(m, rq, "\t\tactive ");
|
|
|
|
drm_printf(m, "\t\tring->start: 0x%08x\n",
|
|
i915_ggtt_offset(rq->ring->vma));
|
|
drm_printf(m, "\t\tring->head: 0x%08x\n",
|
|
rq->ring->head);
|
|
drm_printf(m, "\t\tring->tail: 0x%08x\n",
|
|
rq->ring->tail);
|
|
drm_printf(m, "\t\tring->emit: 0x%08x\n",
|
|
rq->ring->emit);
|
|
drm_printf(m, "\t\tring->space: 0x%08x\n",
|
|
rq->ring->space);
|
|
|
|
if (tl) {
|
|
drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
|
|
tl->hwsp_offset);
|
|
intel_timeline_put(tl);
|
|
}
|
|
|
|
print_request_ring(m, rq);
|
|
|
|
if (rq->hw_context->lrc_reg_state) {
|
|
drm_printf(m, "Logical Ring Context:\n");
|
|
hexdump(m, rq->hw_context->lrc_reg_state, PAGE_SIZE);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&engine->active.lock, flags);
|
|
|
|
drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
|
|
wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
|
|
if (wakeref) {
|
|
intel_engine_print_registers(engine, m);
|
|
intel_runtime_pm_put(engine->uncore->rpm, wakeref);
|
|
} else {
|
|
drm_printf(m, "\tDevice is asleep; skipping register dump\n");
|
|
}
|
|
|
|
intel_execlists_show_requests(engine, m, print_request, 8);
|
|
|
|
drm_printf(m, "HWSP:\n");
|
|
hexdump(m, engine->status_page.addr, PAGE_SIZE);
|
|
|
|
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
|
|
|
|
intel_engine_print_breadcrumbs(engine, m);
|
|
}
|
|
|
|
/**
|
|
* intel_enable_engine_stats() - Enable engine busy tracking on engine
|
|
* @engine: engine to enable stats collection
|
|
*
|
|
* Start collecting the engine busyness data for @engine.
|
|
*
|
|
* Returns 0 on success or a negative error code.
|
|
*/
|
|
int intel_enable_engine_stats(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_engine_execlists *execlists = &engine->execlists;
|
|
unsigned long flags;
|
|
int err = 0;
|
|
|
|
if (!intel_engine_supports_stats(engine))
|
|
return -ENODEV;
|
|
|
|
execlists_active_lock_bh(execlists);
|
|
write_seqlock_irqsave(&engine->stats.lock, flags);
|
|
|
|
if (unlikely(engine->stats.enabled == ~0)) {
|
|
err = -EBUSY;
|
|
goto unlock;
|
|
}
|
|
|
|
if (engine->stats.enabled++ == 0) {
|
|
struct i915_request * const *port;
|
|
struct i915_request *rq;
|
|
|
|
engine->stats.enabled_at = ktime_get();
|
|
|
|
/* XXX submission method oblivious? */
|
|
for (port = execlists->active; (rq = *port); port++)
|
|
engine->stats.active++;
|
|
|
|
for (port = execlists->pending; (rq = *port); port++) {
|
|
/* Exclude any contexts already counted in active */
|
|
if (!intel_context_inflight_count(rq->hw_context))
|
|
engine->stats.active++;
|
|
}
|
|
|
|
if (engine->stats.active)
|
|
engine->stats.start = engine->stats.enabled_at;
|
|
}
|
|
|
|
unlock:
|
|
write_sequnlock_irqrestore(&engine->stats.lock, flags);
|
|
execlists_active_unlock_bh(execlists);
|
|
|
|
return err;
|
|
}
|
|
|
|
static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
|
|
{
|
|
ktime_t total = engine->stats.total;
|
|
|
|
/*
|
|
* If the engine is executing something at the moment
|
|
* add it to the total.
|
|
*/
|
|
if (engine->stats.active)
|
|
total = ktime_add(total,
|
|
ktime_sub(ktime_get(), engine->stats.start));
|
|
|
|
return total;
|
|
}
|
|
|
|
/**
|
|
* intel_engine_get_busy_time() - Return current accumulated engine busyness
|
|
* @engine: engine to report on
|
|
*
|
|
* Returns accumulated time @engine was busy since engine stats were enabled.
|
|
*/
|
|
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
|
|
{
|
|
unsigned int seq;
|
|
ktime_t total;
|
|
|
|
do {
|
|
seq = read_seqbegin(&engine->stats.lock);
|
|
total = __intel_engine_get_busy_time(engine);
|
|
} while (read_seqretry(&engine->stats.lock, seq));
|
|
|
|
return total;
|
|
}
|
|
|
|
/**
|
|
* intel_disable_engine_stats() - Disable engine busy tracking on engine
|
|
* @engine: engine to disable stats collection
|
|
*
|
|
* Stops collecting the engine busyness data for @engine.
|
|
*/
|
|
void intel_disable_engine_stats(struct intel_engine_cs *engine)
|
|
{
|
|
unsigned long flags;
|
|
|
|
if (!intel_engine_supports_stats(engine))
|
|
return;
|
|
|
|
write_seqlock_irqsave(&engine->stats.lock, flags);
|
|
WARN_ON_ONCE(engine->stats.enabled == 0);
|
|
if (--engine->stats.enabled == 0) {
|
|
engine->stats.total = __intel_engine_get_busy_time(engine);
|
|
engine->stats.active = 0;
|
|
}
|
|
write_sequnlock_irqrestore(&engine->stats.lock, flags);
|
|
}
|
|
|
|
static bool match_ring(struct i915_request *rq)
|
|
{
|
|
u32 ring = ENGINE_READ(rq->engine, RING_START);
|
|
|
|
return ring == i915_ggtt_offset(rq->ring->vma);
|
|
}
|
|
|
|
struct i915_request *
|
|
intel_engine_find_active_request(struct intel_engine_cs *engine)
|
|
{
|
|
struct i915_request *request, *active = NULL;
|
|
|
|
/*
|
|
* We are called by the error capture, reset and to dump engine
|
|
* state at random points in time. In particular, note that neither is
|
|
* crucially ordered with an interrupt. After a hang, the GPU is dead
|
|
* and we assume that no more writes can happen (we waited long enough
|
|
* for all writes that were in transaction to be flushed) - adding an
|
|
* extra delay for a recent interrupt is pointless. Hence, we do
|
|
* not need an engine->irq_seqno_barrier() before the seqno reads.
|
|
* At all other times, we must assume the GPU is still running, but
|
|
* we only care about the snapshot of this moment.
|
|
*/
|
|
lockdep_assert_held(&engine->active.lock);
|
|
list_for_each_entry(request, &engine->active.requests, sched.link) {
|
|
if (i915_request_completed(request))
|
|
continue;
|
|
|
|
if (!i915_request_started(request))
|
|
continue;
|
|
|
|
/* More than one preemptible request may match! */
|
|
if (!match_ring(request))
|
|
continue;
|
|
|
|
active = request;
|
|
break;
|
|
}
|
|
|
|
return active;
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
#include "mock_engine.c"
|
|
#include "selftest_engine.c"
|
|
#include "selftest_engine_cs.c"
|
|
#endif
|