584 lines
13 KiB
C
584 lines
13 KiB
C
#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <asm/apicdef.h>
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#include <asm/atomic.h>
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#include <asm/fixmap.h>
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#include <asm/mpspec.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
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extern void generic_apic_probe(void);
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#else
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static inline void generic_apic_probe(void)
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{
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}
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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extern unsigned int apic_verbosity;
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extern int local_apic_timer_c2_ok;
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extern int disable_apic;
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#ifdef CONFIG_SMP
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extern void __inquire_remote_apic(int apicid);
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#else /* CONFIG_SMP */
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static inline void __inquire_remote_apic(int apicid)
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{
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}
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#endif /* CONFIG_SMP */
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static inline void default_inquire_remote_apic(int apicid)
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{
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if (apic_verbosity >= APIC_DEBUG)
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__inquire_remote_apic(apicid);
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}
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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#endif
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#ifdef CONFIG_X86_64
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extern int is_vsmp_box(void);
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#else
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static inline int is_vsmp_box(void)
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{
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return 0;
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}
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#endif
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extern void xapic_wait_icr_idle(void);
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extern u32 safe_xapic_wait_icr_idle(void);
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extern void xapic_icr_write(u32, u32);
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extern int setup_profiling_timer(unsigned int);
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static inline void native_apic_mem_write(u32 reg, u32 v)
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{
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
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ASM_OUTPUT2("=r" (v), "=m" (*addr)),
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ASM_OUTPUT2("0" (v), "m" (*addr)));
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}
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static inline u32 native_apic_mem_read(u32 reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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extern void native_apic_wait_icr_idle(void);
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extern u32 native_safe_apic_wait_icr_idle(void);
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extern void native_apic_icr_write(u32 low, u32 id);
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extern u64 native_apic_icr_read(void);
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#define EIM_8BIT_APIC_ID 0
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#define EIM_32BIT_APIC_ID 1
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#ifdef CONFIG_X86_X2APIC
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/*
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* Make previous memory operations globally visible before
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* sending the IPI through x2apic wrmsr. We need a serializing instruction or
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* mfence for this.
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*/
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static inline void x2apic_wrmsr_fence(void)
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{
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asm volatile("mfence" : : : "memory");
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}
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u32 low, high;
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if (reg == APIC_DFR)
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return -1;
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rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
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return low;
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}
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static inline void native_x2apic_wait_icr_idle(void)
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{
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/* no need to wait for icr idle in x2apic */
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return;
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}
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static inline u32 native_safe_x2apic_wait_icr_idle(void)
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{
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/* no need to wait for icr idle in x2apic */
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return 0;
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}
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static inline void native_x2apic_icr_write(u32 low, u32 id)
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{
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wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
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}
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static inline u64 native_x2apic_icr_read(void)
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{
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unsigned long val;
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rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
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return val;
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}
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extern int x2apic, x2apic_phys;
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extern void check_x2apic(void);
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extern void enable_x2apic(void);
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extern void enable_IR_x2apic(void);
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extern void x2apic_icr_write(u32 low, u32 id);
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static inline int x2apic_enabled(void)
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{
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int msr, msr2;
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if (!cpu_has_x2apic)
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return 0;
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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if (msr & X2APIC_ENABLE)
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return 1;
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return 0;
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}
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#else
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static inline void check_x2apic(void)
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{
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}
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static inline void enable_x2apic(void)
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{
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}
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static inline void enable_IR_x2apic(void)
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{
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}
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static inline int x2apic_enabled(void)
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{
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return 0;
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}
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#define x2apic 0
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#endif
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extern int get_physical_broadcast(void);
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#ifdef CONFIG_X86_X2APIC
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static inline void ack_x2APIC_irq(void)
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{
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/* Docs say use 0 for future compatibility */
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native_apic_msr_write(APIC_EOI, 0);
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}
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#endif
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void end_local_APIC_setup(void);
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extern void init_apic_mappings(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void enable_NMI_through_LVT0(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern void early_init_lapic_mapping(void);
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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#endif
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extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
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extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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static inline void init_apic_mappings(void) { }
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static inline void disable_local_APIC(void) { }
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#ifdef CONFIG_X86_64
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#define SET_APIC_ID(x) (apic->set_apic_id(x))
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#else
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#endif
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/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Generic APIC sub-arch data struct.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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struct apic {
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char *name;
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int (*probe)(void);
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int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
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int (*apic_id_registered)(void);
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u32 irq_delivery_mode;
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u32 irq_dest_mode;
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const struct cpumask *(*target_cpus)(void);
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int disable_esr;
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int dest_logical;
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unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
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unsigned long (*check_apicid_present)(int apicid);
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void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
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void (*init_apic_ldr)(void);
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physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
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void (*setup_apic_routing)(void);
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int (*multi_timer_check)(int apic, int irq);
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int (*apicid_to_node)(int logical_apicid);
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int (*cpu_to_logical_apicid)(int cpu);
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int (*cpu_present_to_apicid)(int mps_cpu);
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physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
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void (*setup_portio_remap)(void);
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int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
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void (*enable_apic_mode)(void);
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int (*phys_pkg_id)(int cpuid_apic, int index_msb);
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/*
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* When one of the next two hooks returns 1 the apic
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* is switched to this. Essentially they are additional
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* probe functions:
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*/
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int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
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unsigned int (*get_apic_id)(unsigned long x);
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unsigned long (*set_apic_id)(unsigned int id);
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unsigned long apic_id_mask;
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unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
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unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
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const struct cpumask *andmask);
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/* ipi */
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void (*send_IPI_mask)(const struct cpumask *mask, int vector);
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void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
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int vector);
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void (*send_IPI_allbutself)(int vector);
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void (*send_IPI_all)(int vector);
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void (*send_IPI_self)(int vector);
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/* wakeup_secondary_cpu */
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int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
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int trampoline_phys_low;
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int trampoline_phys_high;
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void (*wait_for_init_deassert)(atomic_t *deassert);
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void (*smp_callin_clear_local_apic)(void);
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void (*inquire_remote_apic)(int apicid);
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/* apic ops */
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u32 (*read)(u32 reg);
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void (*write)(u32 reg, u32 v);
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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void (*wait_icr_idle)(void);
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u32 (*safe_wait_icr_idle)(void);
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};
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/*
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* Pointer to the local APIC driver in use on this system (there's
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* always just one such driver in use - the kernel decides via an
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* early probing process which one it picks - and then sticks to it):
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*/
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extern struct apic *apic;
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/*
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* APIC functionality to boot other CPUs - only used on SMP:
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*/
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#ifdef CONFIG_SMP
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extern atomic_t init_deasserted;
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extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
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#endif
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static inline u32 apic_read(u32 reg)
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{
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return apic->read(reg);
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}
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static inline void apic_write(u32 reg, u32 val)
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{
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apic->write(reg, val);
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}
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static inline u64 apic_icr_read(void)
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{
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return apic->icr_read();
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}
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static inline void apic_icr_write(u32 low, u32 high)
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{
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apic->icr_write(low, high);
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}
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static inline void apic_wait_icr_idle(void)
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{
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apic->wait_icr_idle();
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}
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static inline u32 safe_apic_wait_icr_idle(void)
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{
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return apic->safe_wait_icr_idle();
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}
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static inline void ack_APIC_irq(void)
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{
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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#endif
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}
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static inline unsigned default_get_apic_id(unsigned long x)
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{
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unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
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if (APIC_XAPIC(ver))
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return (x >> 24) & 0xFF;
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else
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return (x >> 24) & 0x0F;
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}
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/*
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* Warm reset vector default position:
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*/
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#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
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#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
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#ifdef CONFIG_X86_64
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extern struct apic apic_flat;
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extern struct apic apic_physflat;
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extern struct apic apic_x2apic_cluster;
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extern struct apic apic_x2apic_phys;
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extern int default_acpi_madt_oem_check(char *, char *);
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extern void apic_send_IPI_self(int vector);
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extern struct apic apic_x2apic_uv_x;
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DECLARE_PER_CPU(int, x2apic_extra_bits);
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extern int default_cpu_present_to_apicid(int mps_cpu);
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extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
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#endif
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static inline void default_wait_for_init_deassert(atomic_t *deassert)
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{
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while (!atomic_read(deassert))
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cpu_relax();
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return;
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}
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extern void generic_bigsmp_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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static inline const struct cpumask *default_target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_mask;
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#else
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return cpumask_of(0);
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#endif
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}
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DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
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static inline unsigned int read_apic_id(void)
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{
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unsigned int reg;
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reg = apic_read(APIC_ID);
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return apic->get_apic_id(reg);
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}
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extern void default_setup_apic_routing(void);
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#ifdef CONFIG_X86_32
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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extern void default_init_apic_ldr(void);
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static inline int default_apic_id_registered(void)
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{
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return physid_isset(read_apic_id(), phys_cpu_present_map);
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}
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static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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extern int default_apicid_to_node(int logical_apicid);
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#endif
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static inline unsigned int
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default_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
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}
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static inline unsigned int
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default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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unsigned long mask1 = cpumask_bits(cpumask)[0];
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unsigned long mask2 = cpumask_bits(andmask)[0];
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unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
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return (unsigned int)(mask1 & mask2 & mask3);
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}
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static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long default_check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
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{
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return phys_map;
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}
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/* Mapping from cpu number to logical apicid */
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static inline int default_cpu_to_logical_apicid(int cpu)
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{
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return 1 << cpu;
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}
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static inline int __default_cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
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return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
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else
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return BAD_APICID;
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}
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static inline int
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__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
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}
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#ifdef CONFIG_X86_32
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static inline int default_cpu_present_to_apicid(int mps_cpu)
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{
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return __default_cpu_present_to_apicid(mps_cpu);
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}
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static inline int
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default_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
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}
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#else
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extern int default_cpu_present_to_apicid(int mps_cpu);
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extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
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#endif
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static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
|
|
{
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return physid_mask_of_physid(phys_apicid);
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}
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|
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#endif /* CONFIG_X86_LOCAL_APIC */
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|
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#ifdef CONFIG_X86_32
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extern u8 cpu_2_logical_apicid[NR_CPUS];
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#endif
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|
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#endif /* _ASM_X86_APIC_H */
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