519 lines
12 KiB
C
519 lines
12 KiB
C
/*
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* Au12x0/Au1550 PSC ALSA ASoC audio support.
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*
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* (c) 2007-2009 MSC Vertriebsges.m.b.H.,
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* Manuel Lauss <manuel.lauss@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Au1xxx-PSC AC97 glue.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/suspend.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#include "psc.h"
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/* how often to retry failed codec register reads/writes */
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#define AC97_RW_RETRIES 5
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#define AC97_DIR \
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(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
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#define AC97_RATES \
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SNDRV_PCM_RATE_8000_48000
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#define AC97_FMTS \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)
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#define AC97PCR_START(stype) \
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((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
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#define AC97PCR_STOP(stype) \
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((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
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#define AC97PCR_CLRFIFO(stype) \
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((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
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#define AC97STAT_BUSY(stype) \
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((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
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/* instance data. There can be only one, MacLeod!!!! */
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static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
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#if 0
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/* this could theoretically work, but ac97->bus->card->private_data can be NULL
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* when snd_ac97_mixer() is called; I don't know if the rest further down the
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* chain are always valid either.
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*/
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static inline struct au1xpsc_audio_data *ac97_to_pscdata(struct snd_ac97 *x)
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{
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struct snd_soc_card *c = x->bus->card->private_data;
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return snd_soc_dai_get_drvdata(c->rtd->cpu_dai);
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}
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#else
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#define ac97_to_pscdata(x) au1xpsc_ac97_workdata
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#endif
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/* AC97 controller reads codec register */
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static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
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unsigned short retry, tmo;
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unsigned long data;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&pscdata->lock);
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au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
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AC97_CDC(pscdata));
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au_sync();
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tmo = 20;
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do {
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udelay(21);
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if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
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break;
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} while (--tmo);
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data = au_readl(AC97_CDC(pscdata));
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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mutex_unlock(&pscdata->lock);
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if (reg != ((data >> 16) & 0x7f))
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tmo = 1; /* wrong register, try again */
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} while (--retry && !tmo);
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return retry ? data & 0xffff : 0xffff;
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}
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/* AC97 controller writes to codec register */
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static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
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unsigned int tmo, retry;
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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retry = AC97_RW_RETRIES;
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do {
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mutex_lock(&pscdata->lock);
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au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
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AC97_CDC(pscdata));
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au_sync();
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tmo = 20;
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do {
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udelay(21);
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if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
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break;
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} while (--tmo);
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au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
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au_sync();
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mutex_unlock(&pscdata->lock);
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} while (--retry && !tmo);
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}
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/* AC97 controller asserts a warm reset */
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static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
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au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
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au_sync();
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msleep(10);
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au_writel(0, AC97_RST(pscdata));
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au_sync();
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}
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static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
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int i;
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/* disable PSC during cold reset */
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au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
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au_sync();
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/* issue cold reset */
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au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
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au_sync();
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msleep(500);
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au_writel(0, AC97_RST(pscdata));
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au_sync();
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/* enable PSC */
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au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
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au_sync();
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/* wait for PSC to indicate it's ready */
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i = 1000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
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msleep(1);
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if (i == 0) {
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printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
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return;
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}
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/* enable the ac97 function */
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au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* wait for AC97 core to become ready */
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i = 1000;
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while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
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msleep(1);
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if (i == 0)
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printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
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}
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/* AC97 controller operations */
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = au1xpsc_ac97_read,
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.write = au1xpsc_ac97_write,
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.reset = au1xpsc_ac97_cold_reset,
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.warm_reset = au1xpsc_ac97_warm_reset,
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};
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EXPORT_SYMBOL_GPL(soc_ac97_ops);
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static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
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unsigned long r, ro, stat;
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int chans, t, stype = substream->stream;
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chans = params_channels(params);
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r = ro = au_readl(AC97_CFG(pscdata));
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stat = au_readl(AC97_STAT(pscdata));
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/* already active? */
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if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
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/* reject parameters not currently set up */
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if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
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(pscdata->rate != params_rate(params)))
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return -EINVAL;
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} else {
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/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
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r &= ~PSC_AC97CFG_LEN_MASK;
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r |= PSC_AC97CFG_SET_LEN(params->msbits);
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/* channels: enable slots for front L/R channel */
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if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
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r &= ~PSC_AC97CFG_TXSLOT_MASK;
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r |= PSC_AC97CFG_TXSLOT_ENA(3);
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r |= PSC_AC97CFG_TXSLOT_ENA(4);
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} else {
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r &= ~PSC_AC97CFG_RXSLOT_MASK;
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r |= PSC_AC97CFG_RXSLOT_ENA(3);
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r |= PSC_AC97CFG_RXSLOT_ENA(4);
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}
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/* do we need to poke the hardware? */
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if (!(r ^ ro))
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goto out;
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/* ac97 engine is about to be disabled */
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mutex_lock(&pscdata->lock);
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/* disable AC97 device controller first... */
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au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* ...wait for it... */
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t = 100;
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while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
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msleep(1);
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if (!t)
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printk(KERN_ERR "PSC-AC97: can't disable!\n");
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/* ...write config... */
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au_writel(r, AC97_CFG(pscdata));
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au_sync();
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/* ...enable the AC97 controller again... */
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au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
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au_sync();
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/* ...and wait for ready bit */
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t = 100;
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while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
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msleep(1);
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if (!t)
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printk(KERN_ERR "PSC-AC97: can't enable!\n");
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mutex_unlock(&pscdata->lock);
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pscdata->cfg = r;
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pscdata->rate = params_rate(params);
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}
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out:
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return 0;
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}
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static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
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int ret, stype = substream->stream;
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ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
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au_sync();
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au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
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au_sync();
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while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
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asm volatile ("nop");
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au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
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au_sync();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
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return 0;
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}
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static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
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{
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return au1xpsc_ac97_workdata ? 0 : -ENODEV;
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}
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static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
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.startup = au1xpsc_ac97_startup,
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.trigger = au1xpsc_ac97_trigger,
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.hw_params = au1xpsc_ac97_hw_params,
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};
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static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
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.ac97_control = 1,
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.probe = au1xpsc_ac97_probe,
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.playback = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.capture = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.ops = &au1xpsc_ac97_dai_ops,
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};
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static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
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{
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int ret;
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struct resource *iores, *dmares;
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unsigned long sel;
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struct au1xpsc_audio_data *wd;
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wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
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GFP_KERNEL);
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if (!wd)
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return -ENOMEM;
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mutex_init(&wd->lock);
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores)
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return -ENODEV;
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if (!devm_request_mem_region(&pdev->dev, iores->start,
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resource_size(iores),
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pdev->name))
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return -EBUSY;
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wd->mmio = devm_ioremap(&pdev->dev, iores->start,
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resource_size(iores));
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if (!wd->mmio)
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return -EBUSY;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!dmares)
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return -EBUSY;
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wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
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dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (!dmares)
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return -EBUSY;
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wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
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/* configuration: max dma trigger threshold, enable ac97 */
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wd->cfg = PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8 |
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PSC_AC97CFG_DE_ENABLE;
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/* preserve PSC clock source set up by platform */
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sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
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au_sync();
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au_writel(0, PSC_SEL(wd));
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au_sync();
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au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
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au_sync();
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/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
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memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
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sizeof(struct snd_soc_dai_driver));
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wd->dai_drv.name = dev_name(&pdev->dev);
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platform_set_drvdata(pdev, wd);
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ret = snd_soc_register_dai(&pdev->dev, &wd->dai_drv);
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if (ret)
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return ret;
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au1xpsc_ac97_workdata = wd;
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return 0;
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}
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static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
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{
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struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
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snd_soc_unregister_dai(&pdev->dev);
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/* disable PSC completely */
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au_writel(0, AC97_CFG(wd));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
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au_sync();
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au1xpsc_ac97_workdata = NULL; /* MDEV */
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return 0;
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}
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#ifdef CONFIG_PM
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static int au1xpsc_ac97_drvsuspend(struct device *dev)
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{
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struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
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/* save interesting registers and disable PSC */
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wd->pm[0] = au_readl(PSC_SEL(wd));
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au_writel(0, AC97_CFG(wd));
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au_sync();
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au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
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au_sync();
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return 0;
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}
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static int au1xpsc_ac97_drvresume(struct device *dev)
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{
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struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
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/* restore PSC clock config */
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au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
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au_sync();
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/* after this point the ac97 core will cold-reset the codec.
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* During cold-reset the PSC is reinitialized and the last
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* configuration set up in hw_params() is restored.
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*/
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return 0;
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}
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static struct dev_pm_ops au1xpscac97_pmops = {
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.suspend = au1xpsc_ac97_drvsuspend,
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.resume = au1xpsc_ac97_drvresume,
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};
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#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops
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#else
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#define AU1XPSCAC97_PMOPS NULL
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#endif
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static struct platform_driver au1xpsc_ac97_driver = {
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.driver = {
|
|
.name = "au1xpsc_ac97",
|
|
.owner = THIS_MODULE,
|
|
.pm = AU1XPSCAC97_PMOPS,
|
|
},
|
|
.probe = au1xpsc_ac97_drvprobe,
|
|
.remove = au1xpsc_ac97_drvremove,
|
|
};
|
|
|
|
static int __init au1xpsc_ac97_load(void)
|
|
{
|
|
au1xpsc_ac97_workdata = NULL;
|
|
return platform_driver_register(&au1xpsc_ac97_driver);
|
|
}
|
|
|
|
static void __exit au1xpsc_ac97_unload(void)
|
|
{
|
|
platform_driver_unregister(&au1xpsc_ac97_driver);
|
|
}
|
|
|
|
module_init(au1xpsc_ac97_load);
|
|
module_exit(au1xpsc_ac97_unload);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
|
|
MODULE_AUTHOR("Manuel Lauss");
|
|
|