95 lines
1.9 KiB
C
95 lines
1.9 KiB
C
#ifndef _EDAC_MCE_AMD_H
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#define _EDAC_MCE_AMD_H
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#include <linux/notifier.h>
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#include <asm/mce.h>
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#define BIT_64(n) (U64_C(1) << (n))
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#define EC(x) ((x) & 0xffff)
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#define XEC(x, mask) (((x) >> 16) & mask)
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#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
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#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
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#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
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#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
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#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
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#define TT(x) (((x) >> 2) & 0x3)
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#define TT_MSG(x) tt_msgs[TT(x)]
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#define II(x) (((x) >> 2) & 0x3)
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#define II_MSG(x) ii_msgs[II(x)]
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#define LL(x) ((x) & 0x3)
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#define LL_MSG(x) ll_msgs[LL(x)]
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#define TO(x) (((x) >> 8) & 0x1)
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#define TO_MSG(x) to_msgs[TO(x)]
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#define PP(x) (((x) >> 9) & 0x3)
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#define PP_MSG(x) pp_msgs[PP(x)]
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#define R4(x) (((x) >> 4) & 0xf)
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#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
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/*
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* F3x4C bits (MCi_STATUS' high half)
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*/
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#define NBSH_ERR_CPU_VAL BIT(24)
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enum tt_ids {
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TT_INSTR = 0,
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TT_DATA,
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TT_GEN,
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TT_RESV,
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};
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enum ll_ids {
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LL_RESV = 0,
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LL_L1,
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LL_L2,
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LL_LG,
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};
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enum ii_ids {
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II_MEM = 0,
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II_RESV,
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II_IO,
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II_GEN,
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};
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enum rrrr_ids {
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R4_GEN = 0,
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R4_RD,
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R4_WR,
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R4_DRD,
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R4_DWR,
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R4_IRD,
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R4_PREF,
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R4_EVICT,
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R4_SNOOP,
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};
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extern const char *tt_msgs[];
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extern const char *ll_msgs[];
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extern const char *rrrr_msgs[];
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extern const char *pp_msgs[];
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extern const char *to_msgs[];
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extern const char *ii_msgs[];
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/*
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* per-family decoder ops
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*/
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struct amd_decoder_ops {
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bool (*dc_mce)(u16, u8);
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bool (*ic_mce)(u16, u8);
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bool (*nb_mce)(u16, u8);
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};
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void amd_report_gart_errors(bool);
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void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32));
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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32));
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void amd_decode_nb_mce(int, struct mce *, u32);
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int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
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#endif /* _EDAC_MCE_AMD_H */
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