564 lines
17 KiB
C
564 lines
17 KiB
C
/*
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* Broadcom NetXtreme-E RoCE driver.
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*
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
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* Broadcom refers to Broadcom Limited and/or its subsidiaries.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Description: Fast Path Operators (header)
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*/
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#ifndef __BNXT_QPLIB_FP_H__
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#define __BNXT_QPLIB_FP_H__
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struct bnxt_qplib_srq {
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struct bnxt_qplib_pd *pd;
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struct bnxt_qplib_dpi *dpi;
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void __iomem *dbr_base;
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u64 srq_handle;
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u32 id;
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u32 max_wqe;
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u32 max_sge;
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u32 threshold;
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bool arm_req;
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struct bnxt_qplib_cq *cq;
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struct bnxt_qplib_hwq hwq;
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struct bnxt_qplib_swq *swq;
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int start_idx;
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int last_idx;
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struct bnxt_qplib_sg_info sg_info;
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u16 eventq_hw_ring_id;
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spinlock_t lock; /* protect SRQE link list */
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};
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struct bnxt_qplib_sge {
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u64 addr;
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u32 lkey;
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u32 size;
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};
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#define BNXT_QPLIB_MAX_SQE_ENTRY_SIZE sizeof(struct sq_send)
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#define SQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_SQE_ENTRY_SIZE)
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#define SQE_MAX_IDX_PER_PG (SQE_CNT_PER_PG - 1)
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static inline u32 get_sqe_pg(u32 val)
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{
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return ((val & ~SQE_MAX_IDX_PER_PG) / SQE_CNT_PER_PG);
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}
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static inline u32 get_sqe_idx(u32 val)
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{
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return (val & SQE_MAX_IDX_PER_PG);
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}
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#define BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE sizeof(struct sq_psn_search)
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#define PSNE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE)
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#define PSNE_MAX_IDX_PER_PG (PSNE_CNT_PER_PG - 1)
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static inline u32 get_psne_pg(u32 val)
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{
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return ((val & ~PSNE_MAX_IDX_PER_PG) / PSNE_CNT_PER_PG);
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}
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static inline u32 get_psne_idx(u32 val)
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{
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return (val & PSNE_MAX_IDX_PER_PG);
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}
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#define BNXT_QPLIB_QP_MAX_SGL 6
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struct bnxt_qplib_swq {
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u64 wr_id;
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int next_idx;
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u8 type;
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u8 flags;
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u32 start_psn;
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u32 next_psn;
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struct sq_psn_search *psn_search;
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struct sq_psn_search_ext *psn_ext;
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};
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struct bnxt_qplib_swqe {
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/* General */
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#define BNXT_QPLIB_FENCE_WRID 0x46454E43 /* "FENC" */
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u64 wr_id;
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u8 reqs_type;
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u8 type;
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#define BNXT_QPLIB_SWQE_TYPE_SEND 0
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#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM 1
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#define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV 2
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#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE 4
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#define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM 5
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#define BNXT_QPLIB_SWQE_TYPE_RDMA_READ 6
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#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP 8
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#define BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD 11
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#define BNXT_QPLIB_SWQE_TYPE_LOCAL_INV 12
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#define BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR 13
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#define BNXT_QPLIB_SWQE_TYPE_REG_MR 13
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#define BNXT_QPLIB_SWQE_TYPE_BIND_MW 14
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#define BNXT_QPLIB_SWQE_TYPE_RECV 128
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#define BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM 129
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u8 flags;
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#define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP BIT(0)
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#define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE BIT(1)
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#define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE BIT(2)
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#define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT BIT(3)
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#define BNXT_QPLIB_SWQE_FLAGS_INLINE BIT(4)
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struct bnxt_qplib_sge sg_list[BNXT_QPLIB_QP_MAX_SGL];
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int num_sge;
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/* Max inline data is 96 bytes */
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u32 inline_len;
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#define BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH 96
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u8 inline_data[BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH];
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union {
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/* Send, with imm, inval key */
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struct {
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union {
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__be32 imm_data;
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u32 inv_key;
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};
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u32 q_key;
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u32 dst_qp;
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u16 avid;
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} send;
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/* Send Raw Ethernet and QP1 */
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struct {
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u16 lflags;
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u16 cfa_action;
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u32 cfa_meta;
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} rawqp1;
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/* RDMA write, with imm, read */
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struct {
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union {
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__be32 imm_data;
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u32 inv_key;
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};
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u64 remote_va;
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u32 r_key;
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} rdma;
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/* Atomic cmp/swap, fetch/add */
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struct {
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u64 remote_va;
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u32 r_key;
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u64 swap_data;
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u64 cmp_data;
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} atomic;
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/* Local Invalidate */
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struct {
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u32 inv_l_key;
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} local_inv;
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/* FR-PMR */
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struct {
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u8 access_cntl;
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u8 pg_sz_log;
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bool zero_based;
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u32 l_key;
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u32 length;
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u8 pbl_pg_sz_log;
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_4K 0
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_8K 1
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_64K 4
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_256K 6
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_1M 8
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_2M 9
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_4M 10
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#define BNXT_QPLIB_SWQE_PAGE_SIZE_1G 18
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u8 levels;
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#define PAGE_SHIFT_4K 12
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__le64 *pbl_ptr;
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dma_addr_t pbl_dma_ptr;
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u64 *page_list;
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u16 page_list_len;
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u64 va;
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} frmr;
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/* Bind */
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struct {
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u8 access_cntl;
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#define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE BIT(0)
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#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ BIT(1)
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#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE BIT(2)
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#define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC BIT(3)
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#define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND BIT(4)
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bool zero_based;
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u8 mw_type;
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u32 parent_l_key;
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u32 r_key;
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u64 va;
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u32 length;
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} bind;
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};
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};
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#define BNXT_QPLIB_MAX_RQE_ENTRY_SIZE sizeof(struct rq_wqe)
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#define RQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_RQE_ENTRY_SIZE)
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#define RQE_MAX_IDX_PER_PG (RQE_CNT_PER_PG - 1)
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#define RQE_PG(x) (((x) & ~RQE_MAX_IDX_PER_PG) / RQE_CNT_PER_PG)
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#define RQE_IDX(x) ((x) & RQE_MAX_IDX_PER_PG)
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struct bnxt_qplib_q {
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struct bnxt_qplib_hwq hwq;
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struct bnxt_qplib_swq *swq;
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struct bnxt_qplib_sg_info sg_info;
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u32 max_wqe;
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u16 q_full_delta;
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u16 max_sge;
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u32 psn;
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bool condition;
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bool single;
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bool send_phantom;
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u32 phantom_wqe_cnt;
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u32 phantom_cqe_cnt;
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u32 next_cq_cons;
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bool flushed;
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};
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struct bnxt_qplib_qp {
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struct bnxt_qplib_pd *pd;
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struct bnxt_qplib_dpi *dpi;
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struct bnxt_qplib_chip_ctx *cctx;
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u64 qp_handle;
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#define BNXT_QPLIB_QP_ID_INVALID 0xFFFFFFFF
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u32 id;
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u8 type;
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u8 sig_type;
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u32 modify_flags;
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u8 state;
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u8 cur_qp_state;
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u32 max_inline_data;
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u32 mtu;
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u8 path_mtu;
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bool en_sqd_async_notify;
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u16 pkey_index;
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u32 qkey;
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u32 dest_qp_id;
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u8 access;
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u8 timeout;
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u8 retry_cnt;
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u8 rnr_retry;
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u64 wqe_cnt;
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u32 min_rnr_timer;
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u32 max_rd_atomic;
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u32 max_dest_rd_atomic;
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u32 dest_qpn;
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u8 smac[6];
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u16 vlan_id;
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u8 nw_type;
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struct bnxt_qplib_ah ah;
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#define BTH_PSN_MASK ((1 << 24) - 1)
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/* SQ */
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struct bnxt_qplib_q sq;
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/* RQ */
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struct bnxt_qplib_q rq;
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/* SRQ */
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struct bnxt_qplib_srq *srq;
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/* CQ */
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struct bnxt_qplib_cq *scq;
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struct bnxt_qplib_cq *rcq;
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/* IRRQ and ORRQ */
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struct bnxt_qplib_hwq irrq;
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struct bnxt_qplib_hwq orrq;
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/* Header buffer for QP1 */
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int sq_hdr_buf_size;
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int rq_hdr_buf_size;
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/*
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* Buffer space for ETH(14), IP or GRH(40), UDP header(8)
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* and ib_bth + ib_deth (20).
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* Max required is 82 when RoCE V2 is enabled
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*/
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#define BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2 86
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/* Ethernet header = 14 */
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/* ib_grh = 40 (provided by MAD) */
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/* ib_bth + ib_deth = 20 */
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/* MAD = 256 (provided by MAD) */
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/* iCRC = 4 */
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#define BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 14
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#define BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2 512
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#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 20
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#define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 40
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#define BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE 20
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void *sq_hdr_buf;
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dma_addr_t sq_hdr_buf_map;
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void *rq_hdr_buf;
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dma_addr_t rq_hdr_buf_map;
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struct list_head sq_flush;
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struct list_head rq_flush;
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};
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#define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE sizeof(struct cq_base)
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#define CQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_CQE_ENTRY_SIZE)
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#define CQE_MAX_IDX_PER_PG (CQE_CNT_PER_PG - 1)
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#define CQE_PG(x) (((x) & ~CQE_MAX_IDX_PER_PG) / CQE_CNT_PER_PG)
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#define CQE_IDX(x) ((x) & CQE_MAX_IDX_PER_PG)
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#define ROCE_CQE_CMP_V 0
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#define CQE_CMP_VALID(hdr, raw_cons, cp_bit) \
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(!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) == \
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!((raw_cons) & (cp_bit)))
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static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *qplib_q)
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{
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return HWQ_CMP((qplib_q->hwq.prod + qplib_q->q_full_delta),
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&qplib_q->hwq) == HWQ_CMP(qplib_q->hwq.cons,
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&qplib_q->hwq);
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}
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struct bnxt_qplib_cqe {
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u8 status;
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u8 type;
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u8 opcode;
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u32 length;
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u16 cfa_meta;
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u64 wr_id;
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union {
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__be32 immdata;
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u32 invrkey;
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};
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u64 qp_handle;
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u64 mr_handle;
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u16 flags;
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u8 smac[6];
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u32 src_qp;
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u16 raweth_qp1_flags;
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u16 raweth_qp1_errors;
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u16 raweth_qp1_cfa_code;
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u32 raweth_qp1_flags2;
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u32 raweth_qp1_metadata;
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u8 raweth_qp1_payload_offset;
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u16 pkey_index;
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};
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#define BNXT_QPLIB_QUEUE_START_PERIOD 0x01
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struct bnxt_qplib_cq {
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struct bnxt_qplib_dpi *dpi;
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void __iomem *dbr_base;
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u32 max_wqe;
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u32 id;
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u16 count;
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u16 period;
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struct bnxt_qplib_hwq hwq;
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u32 cnq_hw_ring_id;
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struct bnxt_qplib_nq *nq;
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bool resize_in_progress;
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struct bnxt_qplib_sg_info sg_info;
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u64 cq_handle;
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#define CQ_RESIZE_WAIT_TIME_MS 500
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unsigned long flags;
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#define CQ_FLAGS_RESIZE_IN_PROG 1
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wait_queue_head_t waitq;
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struct list_head sqf_head, rqf_head;
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atomic_t arm_state;
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spinlock_t compl_lock; /* synch CQ handlers */
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/* Locking Notes:
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* QP can move to error state from modify_qp, async error event or error
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* CQE as part of poll_cq. When QP is moved to error state, it gets added
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* to two flush lists, one each for SQ and RQ.
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* Each flush list is protected by qplib_cq->flush_lock. Both scq and rcq
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* flush_locks should be acquired when QP is moved to error. The control path
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* operations(modify_qp and async error events) are synchronized with poll_cq
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* using upper level CQ locks (bnxt_re_cq->cq_lock) of both SCQ and RCQ.
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* The qplib_cq->flush_lock is required to synchronize two instances of poll_cq
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* of the same QP while manipulating the flush list.
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*/
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spinlock_t flush_lock; /* QP flush management */
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};
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#define BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE sizeof(struct xrrq_irrq)
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#define BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE sizeof(struct xrrq_orrq)
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#define IRD_LIMIT_TO_IRRQ_SLOTS(x) (2 * (x) + 2)
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#define IRRQ_SLOTS_TO_IRD_LIMIT(s) (((s) >> 1) - 1)
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#define ORD_LIMIT_TO_ORRQ_SLOTS(x) ((x) + 1)
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#define ORRQ_SLOTS_TO_ORD_LIMIT(s) ((s) - 1)
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#define BNXT_QPLIB_MAX_NQE_ENTRY_SIZE sizeof(struct nq_base)
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#define NQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_NQE_ENTRY_SIZE)
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#define NQE_MAX_IDX_PER_PG (NQE_CNT_PER_PG - 1)
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#define NQE_PG(x) (((x) & ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG)
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#define NQE_IDX(x) ((x) & NQE_MAX_IDX_PER_PG)
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#define NQE_CMP_VALID(hdr, raw_cons, cp_bit) \
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(!!(le32_to_cpu((hdr)->info63_v[0]) & NQ_BASE_V) == \
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!((raw_cons) & (cp_bit)))
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#define BNXT_QPLIB_NQE_MAX_CNT (128 * 1024)
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#define NQ_CONS_PCI_BAR_REGION 2
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#define NQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT)
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#define NQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID
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#define NQ_DB_IRQ_DIS CMPL_DOORBELL_MASK
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#define NQ_DB_CP_FLAGS_REARM (NQ_DB_KEY_CP | \
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NQ_DB_IDX_VALID)
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#define NQ_DB_CP_FLAGS (NQ_DB_KEY_CP | \
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NQ_DB_IDX_VALID | \
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NQ_DB_IRQ_DIS)
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static inline void bnxt_qplib_ring_nq_db64(void __iomem *db, u32 index,
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u32 xid, bool arm)
|
|
{
|
|
u64 val;
|
|
|
|
val = xid & DBC_DBC_XID_MASK;
|
|
val |= DBC_DBC_PATH_ROCE;
|
|
val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
|
|
val <<= 32;
|
|
val |= index & DBC_DBC_INDEX_MASK;
|
|
writeq(val, db);
|
|
}
|
|
|
|
static inline void bnxt_qplib_ring_nq_db_rearm(void __iomem *db, u32 raw_cons,
|
|
u32 max_elements, u32 xid,
|
|
bool gen_p5)
|
|
{
|
|
u32 index = raw_cons & (max_elements - 1);
|
|
|
|
if (gen_p5)
|
|
bnxt_qplib_ring_nq_db64(db, index, xid, true);
|
|
else
|
|
writel(NQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK), db);
|
|
}
|
|
|
|
static inline void bnxt_qplib_ring_nq_db(void __iomem *db, u32 raw_cons,
|
|
u32 max_elements, u32 xid,
|
|
bool gen_p5)
|
|
{
|
|
u32 index = raw_cons & (max_elements - 1);
|
|
|
|
if (gen_p5)
|
|
bnxt_qplib_ring_nq_db64(db, index, xid, false);
|
|
else
|
|
writel(NQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK), db);
|
|
}
|
|
|
|
struct bnxt_qplib_nq {
|
|
struct pci_dev *pdev;
|
|
struct bnxt_qplib_res *res;
|
|
|
|
int vector;
|
|
cpumask_t mask;
|
|
int budget;
|
|
bool requested;
|
|
struct tasklet_struct worker;
|
|
struct bnxt_qplib_hwq hwq;
|
|
|
|
u16 bar_reg;
|
|
u32 bar_reg_off;
|
|
u16 ring_id;
|
|
void __iomem *bar_reg_iomem;
|
|
|
|
int (*cqn_handler)(struct bnxt_qplib_nq *nq,
|
|
struct bnxt_qplib_cq *cq);
|
|
int (*srqn_handler)(struct bnxt_qplib_nq *nq,
|
|
struct bnxt_qplib_srq *srq,
|
|
u8 event);
|
|
struct workqueue_struct *cqn_wq;
|
|
char name[32];
|
|
};
|
|
|
|
struct bnxt_qplib_nq_work {
|
|
struct work_struct work;
|
|
struct bnxt_qplib_nq *nq;
|
|
struct bnxt_qplib_cq *cq;
|
|
};
|
|
|
|
void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill);
|
|
void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq);
|
|
int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx,
|
|
int msix_vector, bool need_init);
|
|
int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq,
|
|
int nq_idx, int msix_vector, int bar_reg_offset,
|
|
int (*cqn_handler)(struct bnxt_qplib_nq *nq,
|
|
struct bnxt_qplib_cq *cq),
|
|
int (*srqn_handler)(struct bnxt_qplib_nq *nq,
|
|
struct bnxt_qplib_srq *srq,
|
|
u8 event));
|
|
int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,
|
|
struct bnxt_qplib_srq *srq);
|
|
int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,
|
|
struct bnxt_qplib_srq *srq);
|
|
int bnxt_qplib_query_srq(struct bnxt_qplib_res *res,
|
|
struct bnxt_qplib_srq *srq);
|
|
void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res,
|
|
struct bnxt_qplib_srq *srq);
|
|
int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,
|
|
struct bnxt_qplib_swqe *wqe);
|
|
int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
|
|
void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp);
|
|
void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
|
|
struct bnxt_qplib_qp *qp);
|
|
void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
|
|
struct bnxt_qplib_sge *sge);
|
|
void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
|
|
struct bnxt_qplib_sge *sge);
|
|
u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp);
|
|
dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp,
|
|
u32 index);
|
|
void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,
|
|
struct bnxt_qplib_swqe *wqe);
|
|
void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp);
|
|
int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,
|
|
struct bnxt_qplib_swqe *wqe);
|
|
int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
|
|
int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq);
|
|
int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,
|
|
int num, struct bnxt_qplib_qp **qp);
|
|
bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq);
|
|
void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
|
|
void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
|
|
int bnxt_qplib_alloc_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq);
|
|
void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp);
|
|
void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp,
|
|
unsigned long *flags);
|
|
void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
|
|
unsigned long *flags);
|
|
int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq,
|
|
struct bnxt_qplib_cqe *cqe,
|
|
int num_cqes);
|
|
void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp);
|
|
#endif /* __BNXT_QPLIB_FP_H__ */
|