419 lines
12 KiB
C
419 lines
12 KiB
C
/*
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* Chip-specific setup code for the AT91SAM9G45 family
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*
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* Copyright (C) 2009 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include <mach/at91sam9g45.h>
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#include <mach/at91_aic.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioDE_clk = {
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.name = "pioDE_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk trng_clk = {
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.name = "trng_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb0_clk = {
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.name = "tcb0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhphs_clk = {
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.name = "uhphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* Video decoder clock - Only for sam9m10/sam9m11 */
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static struct clk vdec_clk = {
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.name = "vdec_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_op_clk = {
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.name = "adc_op_clk",
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.type = CLK_TYPE_PERIPHERAL,
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.rate_hz = 13200000,
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};
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/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
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static struct clk aestdessha_clk = {
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.name = "aestdessha_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioDE_clk,
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&trng_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc0_clk,
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&twi0_clk,
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&twi1_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tcb0_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&uhphs_clk,
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&lcdc_clk,
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&ac97_clk,
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&macb_clk,
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&isi_clk,
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&udphs_clk,
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&mmc1_clk,
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&adc_op_clk,
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&aestdessha_clk,
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// irq0
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* One additional fake clock for macb_hclk */
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CLKDEV_CON_ID("hclk", &macb_clk),
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/* One additional fake clock for ohci */
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CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
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CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
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CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
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CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
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CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
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/* more usart lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
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/* more tc lookup table for DT entries */
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CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
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CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
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CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
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/* fake hclk clock */
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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CLKDEV_CON_ID("pioD", &pioDE_clk),
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CLKDEV_CON_ID("pioE", &pioDE_clk),
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/* Fake adc clock */
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CLKDEV_CON_ID("adc_clk", &tsc_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9g45_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
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clk_register(&vdec_clk);
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
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{
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.id = AT91SAM9G45_ID_PIOA,
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.regbase = AT91SAM9G45_BASE_PIOA,
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}, {
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.id = AT91SAM9G45_ID_PIOB,
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.regbase = AT91SAM9G45_BASE_PIOB,
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}, {
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.id = AT91SAM9G45_ID_PIOC,
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.regbase = AT91SAM9G45_BASE_PIOC,
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}, {
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.id = AT91SAM9G45_ID_PIODE,
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.regbase = AT91SAM9G45_BASE_PIOD,
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}, {
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.id = AT91SAM9G45_ID_PIODE,
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.regbase = AT91SAM9G45_BASE_PIOE,
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}
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};
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/* --------------------------------------------------------------------
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* AT91SAM9G45 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9g45_map_io(void)
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{
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at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
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init_consistent_dma_size(SZ_4M);
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}
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static void __init at91sam9g45_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
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at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
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at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
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at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
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at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
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}
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static void __init at91sam9g45_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9g45_restart;
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at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9g45_gpio, 5);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D and E */
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0,
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface 0 */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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0, /* Pulse Width Modulation Controller */
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Host High Speed port */
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3, /* LDC Controller */
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5, /* AC97 Controller */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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2, /* USB Device High speed port */
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0, /* AESTDESSHA Crypto HW Accelerators */
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0, /* Multimedia Card Interface 1 */
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0,
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0, /* Advanced Interrupt Controller (IRQ0) */
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};
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AT91_SOC_START(sam9g45)
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.map_io = at91sam9g45_map_io,
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.default_irq_priority = at91sam9g45_default_irq_priority,
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.ioremap_registers = at91sam9g45_ioremap_registers,
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.register_clocks = at91sam9g45_register_clocks,
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.init = at91sam9g45_initialize,
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AT91_SOC_END
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