300 lines
7.4 KiB
C
300 lines
7.4 KiB
C
/*
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* Sonics Silicon Backplane
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* Broadcom Gigabit Ethernet core driver
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*
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* Copyright 2008, Broadcom Corporation
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* Copyright 2008, Michael Buesch <m@bues.ch>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_driver_gige.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/slab.h>
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/*
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MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
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MODULE_AUTHOR("Michael Buesch");
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MODULE_LICENSE("GPL");
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*/
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static const struct ssb_device_id ssb_gige_tbl[] = {
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SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
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SSB_DEVTABLE_END
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};
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/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
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static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
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{
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return ssb_read8(dev->dev, offset);
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}
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static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
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{
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return ssb_read16(dev->dev, offset);
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}
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static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
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{
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return ssb_read32(dev->dev, offset);
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}
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static inline void gige_write8(struct ssb_gige *dev,
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u16 offset, u8 value)
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{
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ssb_write8(dev->dev, offset, value);
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}
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static inline void gige_write16(struct ssb_gige *dev,
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u16 offset, u16 value)
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{
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ssb_write16(dev->dev, offset, value);
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}
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static inline void gige_write32(struct ssb_gige *dev,
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u16 offset, u32 value)
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{
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ssb_write32(dev->dev, offset, value);
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}
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static inline
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u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
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{
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BUG_ON(offset >= 256);
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return gige_read8(dev, SSB_GIGE_PCICFG + offset);
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}
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static inline
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u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
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{
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BUG_ON(offset >= 256);
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return gige_read16(dev, SSB_GIGE_PCICFG + offset);
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}
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static inline
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u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
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{
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BUG_ON(offset >= 256);
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return gige_read32(dev, SSB_GIGE_PCICFG + offset);
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}
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static inline
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void gige_pcicfg_write8(struct ssb_gige *dev,
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unsigned int offset, u8 value)
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{
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BUG_ON(offset >= 256);
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gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
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}
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static inline
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void gige_pcicfg_write16(struct ssb_gige *dev,
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unsigned int offset, u16 value)
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{
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BUG_ON(offset >= 256);
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gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
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}
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static inline
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void gige_pcicfg_write32(struct ssb_gige *dev,
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unsigned int offset, u32 value)
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{
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BUG_ON(offset >= 256);
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gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
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}
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static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int reg,
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int size, u32 *val)
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{
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struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
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unsigned long flags;
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if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (reg >= 256)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&dev->lock, flags);
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switch (size) {
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case 1:
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*val = gige_pcicfg_read8(dev, reg);
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break;
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case 2:
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*val = gige_pcicfg_read16(dev, reg);
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break;
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case 4:
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*val = gige_pcicfg_read32(dev, reg);
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break;
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default:
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WARN_ON(1);
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}
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spin_unlock_irqrestore(&dev->lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int reg,
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int size, u32 val)
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{
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struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
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unsigned long flags;
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if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (reg >= 256)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&dev->lock, flags);
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switch (size) {
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case 1:
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gige_pcicfg_write8(dev, reg, val);
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break;
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case 2:
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gige_pcicfg_write16(dev, reg, val);
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break;
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case 4:
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gige_pcicfg_write32(dev, reg, val);
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break;
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default:
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WARN_ON(1);
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}
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spin_unlock_irqrestore(&dev->lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int __devinit ssb_gige_probe(struct ssb_device *sdev,
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const struct ssb_device_id *id)
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{
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struct ssb_gige *dev;
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u32 base, tmslow, tmshigh;
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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dev->dev = sdev;
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spin_lock_init(&dev->lock);
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dev->pci_controller.pci_ops = &dev->pci_ops;
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dev->pci_controller.io_resource = &dev->io_resource;
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dev->pci_controller.mem_resource = &dev->mem_resource;
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dev->pci_controller.io_map_base = 0x800;
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dev->pci_ops.read = ssb_gige_pci_read_config;
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dev->pci_ops.write = ssb_gige_pci_write_config;
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dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
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dev->io_resource.start = 0x800;
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dev->io_resource.end = 0x8FF;
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dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
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if (!ssb_device_is_enabled(sdev))
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ssb_device_enable(sdev, 0);
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/* Setup BAR0. This is a 64k MMIO region. */
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base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
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gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
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gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
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dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
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dev->mem_resource.start = base;
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dev->mem_resource.end = base + 0x10000 - 1;
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dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
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/* Enable the memory region. */
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gige_pcicfg_write16(dev, PCI_COMMAND,
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gige_pcicfg_read16(dev, PCI_COMMAND)
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| PCI_COMMAND_MEMORY);
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/* Write flushing is controlled by the Flush Status Control register.
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* We want to flush every register write with a timeout and we want
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* to disable the IRQ mask while flushing to avoid concurrency.
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* Note that automatic write flushing does _not_ work from
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* an IRQ handler. The driver must flush manually by reading a register.
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*/
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gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
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/* Check if we have an RGMII or GMII PHY-bus.
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* On RGMII do not bypass the DLLs */
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tmslow = ssb_read32(sdev, SSB_TMSLOW);
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tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
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if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
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tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
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tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
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dev->has_rgmii = 1;
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} else {
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tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
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tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
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dev->has_rgmii = 0;
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}
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tmslow |= SSB_GIGE_TMSLOW_DLLEN;
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ssb_write32(sdev, SSB_TMSLOW, tmslow);
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ssb_set_drvdata(sdev, dev);
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register_pci_controller(&dev->pci_controller);
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return 0;
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}
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bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
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{
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if (!pdev->resource[0].name)
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return 0;
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return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
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}
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EXPORT_SYMBOL(pdev_is_ssb_gige_core);
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int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
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struct pci_dev *pdev)
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{
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struct ssb_gige *dev = ssb_get_drvdata(sdev);
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struct resource *res;
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if (pdev->bus->ops != &dev->pci_ops) {
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/* The PCI device is not on this SSB GigE bridge device. */
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return -ENODEV;
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}
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/* Fixup the PCI resources. */
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res = &(pdev->resource[0]);
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res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
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res->name = dev->mem_resource.name;
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res->start = dev->mem_resource.start;
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res->end = dev->mem_resource.end;
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/* Fixup interrupt lines. */
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pdev->irq = ssb_mips_irq(sdev) + 2;
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pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
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return 0;
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}
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int ssb_gige_map_irq(struct ssb_device *sdev,
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const struct pci_dev *pdev)
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{
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struct ssb_gige *dev = ssb_get_drvdata(sdev);
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if (pdev->bus->ops != &dev->pci_ops) {
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/* The PCI device is not on this SSB GigE bridge device. */
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return -ENODEV;
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}
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return ssb_mips_irq(sdev) + 2;
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}
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static struct ssb_driver ssb_gige_driver = {
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.name = "BCM-GigE",
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.id_table = ssb_gige_tbl,
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.probe = ssb_gige_probe,
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};
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int ssb_gige_init(void)
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{
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return ssb_driver_register(&ssb_gige_driver);
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}
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