Conor Dooley e77da13b8e riscv: dts: microchip: fix the mpfs' mailbox regs ... The mailbox on PolarFire SoC should really have three reg properties, not two. Without splitting into three sections, the system controller's QSPI cannot be accessed as it sits inside the current first range. The driver & binding have been adapted to account for both two & three ranges, so fix the dts too. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2023-03-15 14:43:48 +00:00
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Makefile	Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"	2023-01-25 11:09:32 +00:00
mpfs-icicle-kit-fabric.dtsi	riscv: dts: microchip: fix the icicle's #pwm-cells	2022-11-14 22:16:03 +00:00
mpfs-icicle-kit.dts	riscv: dts: microchip: fix memory node unit address for icicle	2022-10-31 19:47:07 +00:00
mpfs-m100pfs-fabric.dtsi	riscv: dts: microchip: remove unused pcie clocks	2022-11-17 19:22:44 +00:00
mpfs-m100pfsevp.dts	riscv: dts: microchip: add a devicetree for aries' m100pfsevp	2022-09-27 18:53:58 +01:00
mpfs-polarberry-fabric.dtsi	riscv: dts: microchip: remove unused pcie clocks	2022-11-17 19:22:44 +00:00
mpfs-polarberry.dts	riscv: dts: microchip: mpfs: remove bogus card-detect-delay	2022-08-23 22:15:54 +01:00
mpfs-sev-kit-fabric.dtsi	riscv: dts: microchip: remove pcie node from the sev kit	2022-11-17 19:21:15 +00:00
mpfs-sev-kit.dts	riscv: dts: microchip: add sevkit device tree	2022-09-27 18:53:58 +01:00
mpfs-tysom-m-fabric.dtsi	riscv: dts: microchip: add the Aldec TySoM's devicetree	2023-01-25 11:05:31 +00:00
mpfs-tysom-m.dts	riscv: dts: microchip: add the Aldec TySoM's devicetree	2023-01-25 11:05:31 +00:00
mpfs.dtsi	riscv: dts: microchip: fix the mpfs' mailbox regs	2023-03-15 14:43:48 +00:00