86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Toshiba Visconti PLL controller
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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* Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/toshiba,tmpv770x.h>
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#include "pll.h"
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static DEFINE_SPINLOCK(tmpv770x_pll_lock);
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static const struct visconti_pll_rate_table pipll0_rates[] __initconst = {
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VISCONTI_PLL_RATE(840000000, 0x1, 0x0, 0x1, 0x54, 0x000000, 0x2, 0x1),
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VISCONTI_PLL_RATE(780000000, 0x1, 0x0, 0x1, 0x4e, 0x000000, 0x2, 0x1),
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VISCONTI_PLL_RATE(600000000, 0x1, 0x0, 0x1, 0x3c, 0x000000, 0x2, 0x1),
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{ /* sentinel */ },
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};
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static const struct visconti_pll_rate_table piddrcpll_rates[] __initconst = {
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VISCONTI_PLL_RATE(780000000, 0x1, 0x0, 0x1, 0x4e, 0x000000, 0x2, 0x1),
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VISCONTI_PLL_RATE(760000000, 0x1, 0x0, 0x1, 0x4c, 0x000000, 0x2, 0x1),
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{ /* sentinel */ },
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};
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static const struct visconti_pll_rate_table pivoifpll_rates[] __initconst = {
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VISCONTI_PLL_RATE(165000000, 0x1, 0x0, 0x1, 0x42, 0x000000, 0x4, 0x2),
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VISCONTI_PLL_RATE(148500000, 0x1, 0x1, 0x1, 0x3b, 0x666666, 0x4, 0x2),
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VISCONTI_PLL_RATE(96000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x2),
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VISCONTI_PLL_RATE(74250000, 0x1, 0x1, 0x1, 0x3b, 0x666666, 0x4, 0x4),
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VISCONTI_PLL_RATE(54000000, 0x1, 0x0, 0x1, 0x36, 0x000000, 0x5, 0x4),
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VISCONTI_PLL_RATE(48000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x4),
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VISCONTI_PLL_RATE(35750000, 0x1, 0x1, 0x1, 0x32, 0x0ccccc, 0x7, 0x4),
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{ /* sentinel */ },
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};
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static const struct visconti_pll_rate_table piimgerpll_rates[] __initconst = {
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VISCONTI_PLL_RATE(165000000, 0x1, 0x0, 0x1, 0x42, 0x000000, 0x4, 0x2),
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VISCONTI_PLL_RATE(96000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x2),
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VISCONTI_PLL_RATE(54000000, 0x1, 0x0, 0x1, 0x36, 0x000000, 0x5, 0x4),
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VISCONTI_PLL_RATE(48000000, 0x1, 0x0, 0x1, 0x30, 0x000000, 0x5, 0x4),
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{ /* sentinel */ },
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};
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static const struct visconti_pll_info pll_info[] __initconst = {
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{ TMPV770X_PLL_PIPLL0, "pipll0", "osc2-clk", 0x0, pipll0_rates },
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{ TMPV770X_PLL_PIDDRCPLL, "piddrcpll", "osc2-clk", 0x500, piddrcpll_rates },
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{ TMPV770X_PLL_PIVOIFPLL, "pivoifpll", "osc2-clk", 0x600, pivoifpll_rates },
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{ TMPV770X_PLL_PIIMGERPLL, "piimgerpll", "osc2-clk", 0x700, piimgerpll_rates },
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};
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static void __init tmpv770x_setup_plls(struct device_node *np)
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{
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struct visconti_pll_provider *ctx;
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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return;
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ctx = visconti_init_pll(np, reg_base, TMPV770X_NR_PLL);
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if (IS_ERR(ctx)) {
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iounmap(reg_base);
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return;
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}
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ctx->clk_data.hws[TMPV770X_PLL_PIPLL1] =
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clk_hw_register_fixed_rate(NULL, "pipll1", NULL, 0, 600000000);
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ctx->clk_data.hws[TMPV770X_PLL_PIDNNPLL] =
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clk_hw_register_fixed_rate(NULL, "pidnnpll", NULL, 0, 500000000);
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ctx->clk_data.hws[TMPV770X_PLL_PIETHERPLL] =
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clk_hw_register_fixed_rate(NULL, "pietherpll", NULL, 0, 500000000);
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visconti_register_plls(ctx, pll_info, ARRAY_SIZE(pll_info), &tmpv770x_pll_lock);
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}
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CLK_OF_DECLARE(tmpv770x_plls, "toshiba,tmpv7708-pipllct", tmpv770x_setup_plls);
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