399 lines
9.0 KiB
C
399 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2013, NVIDIA Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <soc/tegra/common.h>
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#include "drm.h"
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#include "gem.h"
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#include "gr2d.h"
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enum {
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RST_MC,
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RST_GR2D,
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RST_GR2D_MAX,
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};
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struct gr2d_soc {
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unsigned int version;
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};
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struct gr2d {
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struct tegra_drm_client client;
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struct host1x_channel *channel;
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struct clk *clk;
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struct reset_control_bulk_data resets[RST_GR2D_MAX];
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unsigned int nresets;
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const struct gr2d_soc *soc;
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DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS);
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};
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static inline struct gr2d *to_gr2d(struct tegra_drm_client *client)
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{
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return container_of(client, struct gr2d, client);
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}
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static int gr2d_init(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
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struct gr2d *gr2d = to_gr2d(drm);
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int err;
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gr2d->channel = host1x_channel_request(client);
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if (!gr2d->channel)
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return -ENOMEM;
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client->syncpts[0] = host1x_syncpt_request(client, flags);
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if (!client->syncpts[0]) {
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err = -ENOMEM;
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dev_err(client->dev, "failed to request syncpoint: %d\n", err);
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goto put;
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}
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err = host1x_client_iommu_attach(client);
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if (err < 0) {
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dev_err(client->dev, "failed to attach to domain: %d\n", err);
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goto free;
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}
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err = tegra_drm_register_client(dev->dev_private, drm);
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if (err < 0) {
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dev_err(client->dev, "failed to register client: %d\n", err);
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goto detach_iommu;
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}
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return 0;
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detach_iommu:
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host1x_client_iommu_detach(client);
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free:
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host1x_syncpt_put(client->syncpts[0]);
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put:
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host1x_channel_put(gr2d->channel);
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return err;
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}
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static int gr2d_exit(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct drm_device *dev = dev_get_drvdata(client->host);
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struct tegra_drm *tegra = dev->dev_private;
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struct gr2d *gr2d = to_gr2d(drm);
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int err;
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err = tegra_drm_unregister_client(tegra, drm);
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if (err < 0)
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return err;
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pm_runtime_dont_use_autosuspend(client->dev);
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pm_runtime_force_suspend(client->dev);
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host1x_client_iommu_detach(client);
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host1x_syncpt_put(client->syncpts[0]);
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host1x_channel_put(gr2d->channel);
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gr2d->channel = NULL;
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return 0;
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}
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static const struct host1x_client_ops gr2d_client_ops = {
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.init = gr2d_init,
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.exit = gr2d_exit,
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};
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static int gr2d_open_channel(struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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struct gr2d *gr2d = to_gr2d(client);
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context->channel = host1x_channel_get(gr2d->channel);
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if (!context->channel)
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return -ENOMEM;
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return 0;
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}
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static void gr2d_close_channel(struct tegra_drm_context *context)
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{
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host1x_channel_put(context->channel);
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}
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static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset)
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{
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struct gr2d *gr2d = dev_get_drvdata(dev);
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switch (class) {
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case HOST1X_CLASS_HOST1X:
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if (offset == 0x2b)
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return 1;
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break;
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case HOST1X_CLASS_GR2D:
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case HOST1X_CLASS_GR2D_SB:
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if (offset >= GR2D_NUM_REGS)
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break;
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if (test_bit(offset, gr2d->addr_regs))
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return 1;
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break;
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}
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return 0;
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}
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static int gr2d_is_valid_class(u32 class)
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{
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return (class == HOST1X_CLASS_GR2D ||
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class == HOST1X_CLASS_GR2D_SB);
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}
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static const struct tegra_drm_client_ops gr2d_ops = {
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.open_channel = gr2d_open_channel,
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.close_channel = gr2d_close_channel,
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.is_addr_reg = gr2d_is_addr_reg,
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.is_valid_class = gr2d_is_valid_class,
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.submit = tegra_drm_submit,
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};
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static const struct gr2d_soc tegra20_gr2d_soc = {
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.version = 0x20,
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};
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static const struct gr2d_soc tegra30_gr2d_soc = {
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.version = 0x30,
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};
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static const struct gr2d_soc tegra114_gr2d_soc = {
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.version = 0x35,
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};
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static const struct of_device_id gr2d_match[] = {
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{ .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc },
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{ .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc },
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{ .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc },
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{ },
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};
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MODULE_DEVICE_TABLE(of, gr2d_match);
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static const u32 gr2d_addr_regs[] = {
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GR2D_UA_BASE_ADDR,
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GR2D_VA_BASE_ADDR,
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GR2D_PAT_BASE_ADDR,
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GR2D_DSTA_BASE_ADDR,
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GR2D_DSTB_BASE_ADDR,
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GR2D_DSTC_BASE_ADDR,
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GR2D_SRCA_BASE_ADDR,
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GR2D_SRCB_BASE_ADDR,
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GR2D_PATBASE_ADDR,
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GR2D_SRC_BASE_ADDR_SB,
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GR2D_DSTA_BASE_ADDR_SB,
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GR2D_DSTB_BASE_ADDR_SB,
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GR2D_UA_BASE_ADDR_SB,
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GR2D_VA_BASE_ADDR_SB,
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};
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static int gr2d_get_resets(struct device *dev, struct gr2d *gr2d)
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{
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int err;
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gr2d->resets[RST_MC].id = "mc";
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gr2d->resets[RST_GR2D].id = "2d";
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gr2d->nresets = RST_GR2D_MAX;
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err = devm_reset_control_bulk_get_optional_exclusive_released(
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dev, gr2d->nresets, gr2d->resets);
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if (err) {
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dev_err(dev, "failed to get reset: %d\n", err);
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return err;
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}
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if (WARN_ON(!gr2d->resets[RST_GR2D].rstc))
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return -ENOENT;
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return 0;
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}
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static int gr2d_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct host1x_syncpt **syncpts;
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struct gr2d *gr2d;
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unsigned int i;
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int err;
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gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL);
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if (!gr2d)
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return -ENOMEM;
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platform_set_drvdata(pdev, gr2d);
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gr2d->soc = of_device_get_match_data(dev);
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syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
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if (!syncpts)
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return -ENOMEM;
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gr2d->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(gr2d->clk)) {
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dev_err(dev, "cannot get clock\n");
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return PTR_ERR(gr2d->clk);
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}
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err = gr2d_get_resets(dev, gr2d);
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if (err)
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return err;
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INIT_LIST_HEAD(&gr2d->client.base.list);
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gr2d->client.base.ops = &gr2d_client_ops;
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gr2d->client.base.dev = dev;
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gr2d->client.base.class = HOST1X_CLASS_GR2D;
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gr2d->client.base.syncpts = syncpts;
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gr2d->client.base.num_syncpts = 1;
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INIT_LIST_HEAD(&gr2d->client.list);
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gr2d->client.version = gr2d->soc->version;
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gr2d->client.ops = &gr2d_ops;
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err = devm_tegra_core_dev_init_opp_table_common(dev);
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if (err)
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return err;
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err = host1x_client_register(&gr2d->client.base);
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if (err < 0) {
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dev_err(dev, "failed to register host1x client: %d\n", err);
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return err;
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}
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/* initialize address register map */
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for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++)
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set_bit(gr2d_addr_regs[i], gr2d->addr_regs);
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return 0;
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}
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static void gr2d_remove(struct platform_device *pdev)
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{
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struct gr2d *gr2d = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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host1x_client_unregister(&gr2d->client.base);
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}
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static int __maybe_unused gr2d_runtime_suspend(struct device *dev)
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{
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struct gr2d *gr2d = dev_get_drvdata(dev);
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int err;
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host1x_channel_stop(gr2d->channel);
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reset_control_bulk_release(gr2d->nresets, gr2d->resets);
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/*
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* GR2D module shouldn't be reset while hardware is idling, otherwise
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* host1x's cmdproc will stuck on trying to access any G2 register
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* after reset. GR2D module could be either hot-reset or reset after
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* power-gating of the HEG partition. Hence we will put in reset only
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* the memory client part of the module, the HEG GENPD will take care
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* of resetting GR2D module across power-gating.
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*
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* On Tegra20 there is no HEG partition, but it's okay to have
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* undetermined h/w state since userspace is expected to reprogram
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* the state on each job submission anyways.
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*/
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err = reset_control_acquire(gr2d->resets[RST_MC].rstc);
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if (err) {
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dev_err(dev, "failed to acquire MC reset: %d\n", err);
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goto acquire_reset;
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}
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err = reset_control_assert(gr2d->resets[RST_MC].rstc);
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reset_control_release(gr2d->resets[RST_MC].rstc);
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if (err) {
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dev_err(dev, "failed to assert MC reset: %d\n", err);
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goto acquire_reset;
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}
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clk_disable_unprepare(gr2d->clk);
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return 0;
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acquire_reset:
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reset_control_bulk_acquire(gr2d->nresets, gr2d->resets);
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reset_control_bulk_deassert(gr2d->nresets, gr2d->resets);
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return err;
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}
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static int __maybe_unused gr2d_runtime_resume(struct device *dev)
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{
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struct gr2d *gr2d = dev_get_drvdata(dev);
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int err;
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err = reset_control_bulk_acquire(gr2d->nresets, gr2d->resets);
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if (err) {
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dev_err(dev, "failed to acquire reset: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(gr2d->clk);
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if (err) {
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dev_err(dev, "failed to enable clock: %d\n", err);
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goto release_reset;
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}
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usleep_range(2000, 4000);
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/* this is a reset array which deasserts both 2D MC and 2D itself */
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err = reset_control_bulk_deassert(gr2d->nresets, gr2d->resets);
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if (err) {
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dev_err(dev, "failed to deassert reset: %d\n", err);
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goto disable_clk;
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}
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pm_runtime_enable(dev);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_autosuspend_delay(dev, 500);
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return 0;
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disable_clk:
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clk_disable_unprepare(gr2d->clk);
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release_reset:
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reset_control_bulk_release(gr2d->nresets, gr2d->resets);
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return err;
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}
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static const struct dev_pm_ops tegra_gr2d_pm = {
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SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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struct platform_driver tegra_gr2d_driver = {
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.driver = {
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.name = "tegra-gr2d",
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.of_match_table = gr2d_match,
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.pm = &tegra_gr2d_pm,
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},
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.probe = gr2d_probe,
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.remove_new = gr2d_remove,
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};
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