337 lines
10 KiB
C
337 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include <drm/drm_fourcc.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include "mtk_disp_drv.h"
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#include "mtk_drm_drv.h"
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#include "mtk_mdp_rdma.h"
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#define MDP_RDMA_EN 0x000
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#define FLD_ROT_ENABLE BIT(0)
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#define MDP_RDMA_RESET 0x008
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#define MDP_RDMA_CON 0x020
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#define FLD_OUTPUT_10B BIT(5)
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#define FLD_SIMPLE_MODE BIT(4)
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#define MDP_RDMA_GMCIF_CON 0x028
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#define FLD_COMMAND_DIV BIT(0)
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#define FLD_EXT_PREULTRA_EN BIT(3)
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#define FLD_RD_REQ_TYPE GENMASK(7, 4)
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#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
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#define FLD_ULTRA_EN GENMASK(13, 12)
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#define VAL_ULTRA_EN_ENABLE 1
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#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
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#define VAL_PRE_ULTRA_EN_ENABLE 1
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#define FLD_EXT_ULTRA_EN BIT(18)
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#define MDP_RDMA_SRC_CON 0x030
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#define FLD_OUTPUT_ARGB BIT(25)
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#define FLD_BIT_NUMBER GENMASK(19, 18)
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#define FLD_SWAP BIT(14)
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#define FLD_UNIFORM_CONFIG BIT(17)
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#define RDMA_INPUT_10BIT BIT(18)
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#define FLD_SRC_FORMAT GENMASK(3, 0)
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#define MDP_RDMA_COMP_CON 0x038
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#define FLD_AFBC_EN BIT(22)
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#define FLD_AFBC_YUV_TRANSFORM BIT(21)
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#define FLD_UFBDC_EN BIT(12)
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#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
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#define FLD_MF_BKGD_WB GENMASK(22, 0)
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#define MDP_RDMA_MF_SRC_SIZE 0x070
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#define FLD_MF_SRC_H GENMASK(30, 16)
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#define FLD_MF_SRC_W GENMASK(14, 0)
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#define MDP_RDMA_MF_CLIP_SIZE 0x078
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#define FLD_MF_CLIP_H GENMASK(30, 16)
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#define FLD_MF_CLIP_W GENMASK(14, 0)
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#define MDP_RDMA_SRC_OFFSET_0 0x118
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#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
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#define MDP_RDMA_TRANSFORM_0 0x200
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#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
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#define FLD_TRANS_EN BIT(16)
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#define MDP_RDMA_SRC_BASE_0 0xf00
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#define FLD_SRC_BASE_0 GENMASK(31, 0)
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#define RDMA_CSC_FULL709_TO_RGB 5
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#define RDMA_CSC_BT601_TO_RGB 6
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static const u32 formats[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_BGRX8888,
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DRM_FORMAT_BGRA8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_YUYV,
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};
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enum rdma_format {
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RDMA_INPUT_FORMAT_RGB565 = 0,
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RDMA_INPUT_FORMAT_RGB888 = 1,
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RDMA_INPUT_FORMAT_RGBA8888 = 2,
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RDMA_INPUT_FORMAT_ARGB8888 = 3,
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RDMA_INPUT_FORMAT_UYVY = 4,
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RDMA_INPUT_FORMAT_YUY2 = 5,
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RDMA_INPUT_FORMAT_Y8 = 7,
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RDMA_INPUT_FORMAT_YV12 = 8,
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RDMA_INPUT_FORMAT_UYVY_3PL = 9,
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RDMA_INPUT_FORMAT_NV12 = 12,
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RDMA_INPUT_FORMAT_UYVY_2PL = 13,
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RDMA_INPUT_FORMAT_Y410 = 14
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};
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struct mtk_mdp_rdma {
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void __iomem *regs;
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struct clk *clk;
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struct cmdq_client_reg cmdq_reg;
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};
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static unsigned int rdma_fmt_convert(unsigned int fmt)
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{
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switch (fmt) {
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default:
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case DRM_FORMAT_RGB565:
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return RDMA_INPUT_FORMAT_RGB565;
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case DRM_FORMAT_BGR565:
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return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
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case DRM_FORMAT_RGB888:
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return RDMA_INPUT_FORMAT_RGB888;
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case DRM_FORMAT_BGR888:
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return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_RGBA8888:
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return RDMA_INPUT_FORMAT_ARGB8888;
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_BGRA8888:
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return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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return RDMA_INPUT_FORMAT_RGBA8888;
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
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case DRM_FORMAT_ABGR2101010:
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return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
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case DRM_FORMAT_ARGB2101010:
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return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
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case DRM_FORMAT_RGBA1010102:
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return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
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case DRM_FORMAT_BGRA1010102:
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return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
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case DRM_FORMAT_UYVY:
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return RDMA_INPUT_FORMAT_UYVY;
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case DRM_FORMAT_YUYV:
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return RDMA_INPUT_FORMAT_YUY2;
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}
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}
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static unsigned int rdma_color_convert(unsigned int color_encoding)
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{
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switch (color_encoding) {
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default:
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case DRM_COLOR_YCBCR_BT709:
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return RDMA_CSC_FULL709_TO_RGB;
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case DRM_COLOR_YCBCR_BT601:
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return RDMA_CSC_BT601_TO_RGB;
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}
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}
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static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
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mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
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VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
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FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
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priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
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FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
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FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
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}
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void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
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mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
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priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
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}
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void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
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mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
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priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
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mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
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mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
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}
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void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
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struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
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const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
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bool csc_enable = fmt_info->is_yuv ? true : false;
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unsigned int src_pitch_y = cfg->pitch;
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unsigned int offset_y = 0;
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mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
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mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
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mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
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MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
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if (!csc_enable && fmt_info->has_alpha)
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mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
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priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
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else
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mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
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mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
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mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
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mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
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FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
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mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_CON, FLD_OUTPUT_10B);
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mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_CON, FLD_SIMPLE_MODE);
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if (csc_enable)
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mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,
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&priv->cmdq_reg, priv->regs, MDP_RDMA_TRANSFORM_0,
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FLD_INT_MATRIX_SEL);
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mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
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offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
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mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
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mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
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mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
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mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
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mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
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MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
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}
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const u32 *mtk_mdp_rdma_get_formats(struct device *dev)
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{
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return formats;
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}
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size_t mtk_mdp_rdma_get_num_formats(struct device *dev)
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{
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return ARRAY_SIZE(formats);
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}
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int mtk_mdp_rdma_clk_enable(struct device *dev)
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{
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struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
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return clk_prepare_enable(rdma->clk);
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}
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void mtk_mdp_rdma_clk_disable(struct device *dev)
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{
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struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
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clk_disable_unprepare(rdma->clk);
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}
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static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
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void *data)
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{
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return 0;
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}
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static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
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void *data)
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{
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}
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static const struct component_ops mtk_mdp_rdma_component_ops = {
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.bind = mtk_mdp_rdma_bind,
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.unbind = mtk_mdp_rdma_unbind,
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};
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static int mtk_mdp_rdma_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct mtk_mdp_rdma *priv;
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int ret = 0;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->regs)) {
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dev_err(dev, "failed to ioremap rdma\n");
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return PTR_ERR(priv->regs);
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}
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "failed to get rdma clk\n");
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return PTR_ERR(priv->clk);
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
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if (ret)
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dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
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#endif
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platform_set_drvdata(pdev, priv);
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pm_runtime_enable(dev);
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ret = component_add(dev, &mtk_mdp_rdma_component_ops);
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if (ret != 0) {
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pm_runtime_disable(dev);
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dev_err(dev, "Failed to add component: %d\n", ret);
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}
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return ret;
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}
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static void mtk_mdp_rdma_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
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pm_runtime_disable(&pdev->dev);
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}
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static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
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{ .compatible = "mediatek,mt8195-vdo1-rdma", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
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struct platform_driver mtk_mdp_rdma_driver = {
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.probe = mtk_mdp_rdma_probe,
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.remove_new = mtk_mdp_rdma_remove,
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.driver = {
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.name = "mediatek-mdp-rdma",
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.owner = THIS_MODULE,
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.of_match_table = mtk_mdp_rdma_driver_dt_match,
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},
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};
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