610 lines
18 KiB
C
610 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Authors:
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* YT Shen <yt.shen@mediatek.com>
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* CK Hu <ck.hu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <drm/drm_print.h>
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#include "mtk_disp_drv.h"
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#include "mtk_drm_drv.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_crtc.h"
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#define DISP_REG_DITHER_EN 0x0000
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#define DITHER_EN BIT(0)
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#define DISP_REG_DITHER_CFG 0x0020
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#define DITHER_RELAY_MODE BIT(0)
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#define DITHER_ENGINE_EN BIT(1)
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#define DISP_DITHERING BIT(2)
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#define DISP_REG_DITHER_SIZE 0x0030
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#define DISP_REG_DITHER_5 0x0114
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#define DISP_REG_DITHER_7 0x011c
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#define DISP_REG_DITHER_15 0x013c
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#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
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#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
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#define DITHER_NEW_BIT_MODE BIT(0)
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#define DISP_REG_DITHER_16 0x0140
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#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
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#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
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#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
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#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
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#define DISP_REG_DSC_CON 0x0000
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#define DSC_EN BIT(0)
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#define DSC_DUAL_INOUT BIT(2)
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#define DSC_BYPASS BIT(4)
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#define DSC_UFOE_SEL BIT(16)
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#define DISP_REG_OD_EN 0x0000
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#define DISP_REG_OD_CFG 0x0020
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#define OD_RELAYMODE BIT(0)
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#define DISP_REG_OD_SIZE 0x0030
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#define DISP_REG_POSTMASK_EN 0x0000
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#define POSTMASK_EN BIT(0)
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#define DISP_REG_POSTMASK_CFG 0x0020
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#define POSTMASK_RELAY_MODE BIT(0)
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#define DISP_REG_POSTMASK_SIZE 0x0030
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#define DISP_REG_UFO_START 0x0000
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#define UFO_BYPASS BIT(2)
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struct mtk_ddp_comp_dev {
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struct clk *clk;
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void __iomem *regs;
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struct cmdq_client_reg cmdq_reg;
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};
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void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
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struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
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unsigned int offset)
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{
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (cmdq_pkt)
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cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
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cmdq_reg->offset + offset, value);
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else
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#endif
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writel(value, regs + offset);
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}
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void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
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struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
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unsigned int offset)
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{
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (cmdq_pkt)
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cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
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cmdq_reg->offset + offset, value);
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else
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#endif
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writel_relaxed(value, regs + offset);
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}
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void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
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struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
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unsigned int offset, unsigned int mask)
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{
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (cmdq_pkt) {
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cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
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cmdq_reg->offset + offset, value, mask);
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} else {
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#endif
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u32 tmp = readl(regs + offset);
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tmp = (tmp & ~mask) | (value & mask);
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writel(tmp, regs + offset);
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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}
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#endif
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}
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static int mtk_ddp_clk_enable(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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return clk_prepare_enable(priv->clk);
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}
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static void mtk_ddp_clk_disable(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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clk_disable_unprepare(priv->clk);
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}
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void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
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unsigned int bpc, unsigned int cfg,
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unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
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{
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/* If bpc equal to 0, the dithering function didn't be enabled */
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if (bpc == 0)
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return;
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if (bpc >= MTK_MIN_BPC) {
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mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
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mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
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mtk_ddp_write(cmdq_pkt,
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DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_NEW_BIT_MODE,
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cmdq_reg, regs, DISP_REG_DITHER_15);
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mtk_ddp_write(cmdq_pkt,
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DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
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cmdq_reg, regs, DISP_REG_DITHER_16);
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mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
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}
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}
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static void mtk_dither_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
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mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
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DISP_REG_DITHER_CFG);
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mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
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DITHER_ENGINE_EN, cmdq_pkt);
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}
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static void mtk_dither_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_dither_stop(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
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}
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static void mtk_dither_set(struct device *dev, unsigned int bpc,
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unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
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DISP_DITHERING, cmdq_pkt);
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}
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static void mtk_dsc_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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/* dsc bypass mode */
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mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
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DISP_REG_DSC_CON, DSC_BYPASS);
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mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
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DISP_REG_DSC_CON, DSC_UFOE_SEL);
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mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
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DISP_REG_DSC_CON, DSC_DUAL_INOUT);
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}
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static void mtk_dsc_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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/* write with mask to reserve the value set in mtk_dsc_config */
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mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
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}
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static void mtk_dsc_stop(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
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}
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static void mtk_od_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
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mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
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mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
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}
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static void mtk_od_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(1, priv->regs + DISP_REG_OD_EN);
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}
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static void mtk_postmask_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
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DISP_REG_POSTMASK_SIZE);
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mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
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priv->regs, DISP_REG_POSTMASK_CFG);
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}
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static void mtk_postmask_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
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}
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static void mtk_postmask_stop(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
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}
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static void mtk_ufoe_start(struct device *dev)
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{
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struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
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writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
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}
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static const struct mtk_ddp_comp_funcs ddp_aal = {
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.clk_enable = mtk_aal_clk_enable,
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.clk_disable = mtk_aal_clk_disable,
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.gamma_set = mtk_aal_gamma_set,
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.config = mtk_aal_config,
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.start = mtk_aal_start,
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.stop = mtk_aal_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_ccorr = {
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.clk_enable = mtk_ccorr_clk_enable,
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.clk_disable = mtk_ccorr_clk_disable,
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.config = mtk_ccorr_config,
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.start = mtk_ccorr_start,
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.stop = mtk_ccorr_stop,
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.ctm_set = mtk_ccorr_ctm_set,
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};
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static const struct mtk_ddp_comp_funcs ddp_color = {
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.clk_enable = mtk_color_clk_enable,
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.clk_disable = mtk_color_clk_disable,
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.config = mtk_color_config,
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.start = mtk_color_start,
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};
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static const struct mtk_ddp_comp_funcs ddp_dither = {
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.clk_enable = mtk_ddp_clk_enable,
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.clk_disable = mtk_ddp_clk_disable,
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.config = mtk_dither_config,
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.start = mtk_dither_start,
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.stop = mtk_dither_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_dpi = {
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.start = mtk_dpi_start,
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.stop = mtk_dpi_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_dsc = {
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.clk_enable = mtk_ddp_clk_enable,
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.clk_disable = mtk_ddp_clk_disable,
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.config = mtk_dsc_config,
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.start = mtk_dsc_start,
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.stop = mtk_dsc_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_dsi = {
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.start = mtk_dsi_ddp_start,
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.stop = mtk_dsi_ddp_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_gamma = {
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.clk_enable = mtk_gamma_clk_enable,
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.clk_disable = mtk_gamma_clk_disable,
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.gamma_set = mtk_gamma_set,
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.config = mtk_gamma_config,
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.start = mtk_gamma_start,
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.stop = mtk_gamma_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_merge = {
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.clk_enable = mtk_merge_clk_enable,
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.clk_disable = mtk_merge_clk_disable,
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.start = mtk_merge_start,
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.stop = mtk_merge_stop,
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.config = mtk_merge_config,
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};
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static const struct mtk_ddp_comp_funcs ddp_od = {
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.clk_enable = mtk_ddp_clk_enable,
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.clk_disable = mtk_ddp_clk_disable,
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.config = mtk_od_config,
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.start = mtk_od_start,
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};
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static const struct mtk_ddp_comp_funcs ddp_ovl = {
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.clk_enable = mtk_ovl_clk_enable,
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.clk_disable = mtk_ovl_clk_disable,
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.config = mtk_ovl_config,
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.start = mtk_ovl_start,
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.stop = mtk_ovl_stop,
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.register_vblank_cb = mtk_ovl_register_vblank_cb,
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.unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
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.enable_vblank = mtk_ovl_enable_vblank,
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.disable_vblank = mtk_ovl_disable_vblank,
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.supported_rotations = mtk_ovl_supported_rotations,
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.layer_nr = mtk_ovl_layer_nr,
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.layer_check = mtk_ovl_layer_check,
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.layer_config = mtk_ovl_layer_config,
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.bgclr_in_on = mtk_ovl_bgclr_in_on,
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.bgclr_in_off = mtk_ovl_bgclr_in_off,
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.get_formats = mtk_ovl_get_formats,
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.get_num_formats = mtk_ovl_get_num_formats,
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};
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static const struct mtk_ddp_comp_funcs ddp_postmask = {
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.clk_enable = mtk_ddp_clk_enable,
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.clk_disable = mtk_ddp_clk_disable,
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.config = mtk_postmask_config,
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.start = mtk_postmask_start,
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.stop = mtk_postmask_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_rdma = {
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.clk_enable = mtk_rdma_clk_enable,
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.clk_disable = mtk_rdma_clk_disable,
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.config = mtk_rdma_config,
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.start = mtk_rdma_start,
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.stop = mtk_rdma_stop,
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.register_vblank_cb = mtk_rdma_register_vblank_cb,
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.unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
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.enable_vblank = mtk_rdma_enable_vblank,
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.disable_vblank = mtk_rdma_disable_vblank,
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.layer_nr = mtk_rdma_layer_nr,
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.layer_config = mtk_rdma_layer_config,
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.get_formats = mtk_rdma_get_formats,
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.get_num_formats = mtk_rdma_get_num_formats,
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};
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static const struct mtk_ddp_comp_funcs ddp_ufoe = {
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.clk_enable = mtk_ddp_clk_enable,
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.clk_disable = mtk_ddp_clk_disable,
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.start = mtk_ufoe_start,
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};
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static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
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.clk_enable = mtk_ovl_adaptor_clk_enable,
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.clk_disable = mtk_ovl_adaptor_clk_disable,
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.config = mtk_ovl_adaptor_config,
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.start = mtk_ovl_adaptor_start,
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.stop = mtk_ovl_adaptor_stop,
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.layer_nr = mtk_ovl_adaptor_layer_nr,
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.layer_config = mtk_ovl_adaptor_layer_config,
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.register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
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.unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
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.enable_vblank = mtk_ovl_adaptor_enable_vblank,
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.disable_vblank = mtk_ovl_adaptor_disable_vblank,
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.dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
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.connect = mtk_ovl_adaptor_connect,
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.disconnect = mtk_ovl_adaptor_disconnect,
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.add = mtk_ovl_adaptor_add_comp,
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.remove = mtk_ovl_adaptor_remove_comp,
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.get_formats = mtk_ovl_adaptor_get_formats,
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.get_num_formats = mtk_ovl_adaptor_get_num_formats,
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};
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static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
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[MTK_DISP_AAL] = "aal",
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[MTK_DISP_BLS] = "bls",
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[MTK_DISP_CCORR] = "ccorr",
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[MTK_DISP_COLOR] = "color",
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[MTK_DISP_DITHER] = "dither",
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[MTK_DISP_DSC] = "dsc",
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[MTK_DISP_GAMMA] = "gamma",
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[MTK_DISP_MERGE] = "merge",
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[MTK_DISP_MUTEX] = "mutex",
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[MTK_DISP_OD] = "od",
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[MTK_DISP_OVL] = "ovl",
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[MTK_DISP_OVL_2L] = "ovl-2l",
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[MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
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[MTK_DISP_POSTMASK] = "postmask",
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[MTK_DISP_PWM] = "pwm",
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[MTK_DISP_RDMA] = "rdma",
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[MTK_DISP_UFOE] = "ufoe",
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[MTK_DISP_WDMA] = "wdma",
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[MTK_DP_INTF] = "dp-intf",
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[MTK_DPI] = "dpi",
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[MTK_DSI] = "dsi",
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};
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struct mtk_ddp_comp_match {
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enum mtk_ddp_comp_type type;
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int alias_id;
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const struct mtk_ddp_comp_funcs *funcs;
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};
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static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
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[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
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[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
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[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
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[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
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[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
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[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
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[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
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[DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
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[DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
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[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
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[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
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[DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
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[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
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[DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
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[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
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[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
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[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
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[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
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[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
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[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
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[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
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[DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
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[DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
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[DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
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[DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
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[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
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[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
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[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
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[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
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[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
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[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
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[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
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[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
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[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
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[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
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[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
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[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
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[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
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[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
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[DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
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[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
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[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
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[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
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};
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static bool mtk_drm_find_comp_in_ddp(struct device *dev,
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const unsigned int *path,
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unsigned int path_len,
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struct mtk_ddp_comp *ddp_comp)
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{
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unsigned int i;
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if (path == NULL)
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return false;
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for (i = 0U; i < path_len; i++)
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if (dev == ddp_comp[path[i]].dev)
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return true;
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return false;
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}
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type)
|
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{
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int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
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int i;
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for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
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if (comp_type == mtk_ddp_matches[i].type &&
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(id < 0 || id == mtk_ddp_matches[i].alias_id))
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return i;
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}
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return -EINVAL;
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}
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unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
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struct device *dev)
|
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{
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struct mtk_drm_private *private = drm->dev_private;
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unsigned int ret = 0;
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if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
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private->ddp_comp))
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ret = BIT(0);
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else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
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private->data->ext_len, private->ddp_comp))
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ret = BIT(1);
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else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
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private->data->third_len, private->ddp_comp))
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ret = BIT(2);
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else
|
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DRM_INFO("Failed to find comp in ddp table\n");
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|
|
|
return ret;
|
|
}
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|
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int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
|
|
unsigned int comp_id)
|
|
{
|
|
struct platform_device *comp_pdev;
|
|
enum mtk_ddp_comp_type type;
|
|
struct mtk_ddp_comp_dev *priv;
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
int ret;
|
|
#endif
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|
|
|
if (comp_id < 0 || comp_id >= DDP_COMPONENT_DRM_ID_MAX)
|
|
return -EINVAL;
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|
|
|
type = mtk_ddp_matches[comp_id].type;
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|
|
|
comp->id = comp_id;
|
|
comp->funcs = mtk_ddp_matches[comp_id].funcs;
|
|
/* Not all drm components have a DTS device node, such as ovl_adaptor,
|
|
* which is the drm bring up sub driver
|
|
*/
|
|
if (!node)
|
|
return 0;
|
|
|
|
comp_pdev = of_find_device_by_node(node);
|
|
if (!comp_pdev) {
|
|
DRM_INFO("Waiting for device %s\n", node->full_name);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
comp->dev = &comp_pdev->dev;
|
|
|
|
if (type == MTK_DISP_AAL ||
|
|
type == MTK_DISP_BLS ||
|
|
type == MTK_DISP_CCORR ||
|
|
type == MTK_DISP_COLOR ||
|
|
type == MTK_DISP_GAMMA ||
|
|
type == MTK_DISP_MERGE ||
|
|
type == MTK_DISP_OVL ||
|
|
type == MTK_DISP_OVL_2L ||
|
|
type == MTK_DISP_PWM ||
|
|
type == MTK_DISP_RDMA ||
|
|
type == MTK_DPI ||
|
|
type == MTK_DP_INTF ||
|
|
type == MTK_DSI)
|
|
return 0;
|
|
|
|
priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->regs = of_iomap(node, 0);
|
|
priv->clk = of_clk_get(node, 0);
|
|
if (IS_ERR(priv->clk))
|
|
return PTR_ERR(priv->clk);
|
|
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
|
|
if (ret)
|
|
dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
|
|
#endif
|
|
|
|
platform_set_drvdata(comp_pdev, priv);
|
|
|
|
return 0;
|
|
}
|