OpenCloudOS-Kernel/drivers/cxl/core
Yao Xingtao 843836bfc1 cxl/region: check interleave capability
[ Upstream commit 84328c5acebc10c8cdcf17283ab6c6d548885bfc ]

Since interleave capability is not verified, if the interleave
capability of a target does not match the region need, committing decoder
should have failed at the device end.

In order to checkout this error as quickly as possible, driver needs
to check the interleave capability of target during attaching it to
region.

Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register),
bits 11 and 12 indicate the capability to establish interleaving in 3, 6,
12 and 16 ways. If these bits are not set, the target cannot be attached to
a region utilizing such interleave ways.

Additionally, bits 8 and 9 represent the capability of the bits used for
interleaving in the address, Linux tracks this in the cxl_port
interleave_mask.

Per CXL specification r3.1(8.2.4.20.13 Decoder Protection):
  eIW means encoded Interleave Ways.
  eIG means encoded Interleave Granularity.

  in HPA:
  if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used,
  the interleave bits are none, the following check is ignored.

  if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW + 8 - 1.

  if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW - 1.

  if the interleave mask is insufficient to cover the required interleave
  bits, the target cannot be attached to the region.

Fixes: 384e624bb2 ("cxl/region: Attach endpoint decoders")
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240614084755.59503-2-yaoxt.fnst@fujitsu.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-07-05 09:34:07 +02:00
..
Makefile cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
core.h cxl/region: Move cxl_dpa_to_region() work to the region driver 2024-07-05 09:34:06 +02:00
hdm.c cxl/region: check interleave capability 2024-07-05 09:34:07 +02:00
mbox.c cxl/core: Fix potential payload size confusion in cxl_mem_get_poison() 2024-05-02 16:32:35 +02:00
memdev.c cxl/region: Move cxl_dpa_to_region() work to the region driver 2024-07-05 09:34:06 +02:00
pci.c cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window 2024-03-01 13:34:59 +01:00
pmem.c cxl/memdev: Formalize endpoint port linkage 2023-06-25 14:31:33 -07:00
pmu.c cxl/pmu: Ensure put_device on pmu devices 2024-01-10 17:16:59 +01:00
port.c cxl/port: Fix missing target list lock 2024-01-25 15:35:55 -08:00
region.c cxl/region: check interleave capability 2024-07-05 09:34:07 +02:00
regs.c cxl/core/regs: Fix usage of map->reg_type in cxl_decode_regblock() before assigned 2024-04-17 11:19:27 +02:00
suspend.c PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
trace.c cxl/trace: Add an HPA to cxl_poison trace events 2023-04-23 11:46:13 -07:00
trace.h cxl/trace: Correct DPA field masks for general_media & dram events 2024-06-12 11:12:42 +02:00