OpenCloudOS-Kernel/drivers/cxl
Yao Xingtao 843836bfc1 cxl/region: check interleave capability
[ Upstream commit 84328c5acebc10c8cdcf17283ab6c6d548885bfc ]

Since interleave capability is not verified, if the interleave
capability of a target does not match the region need, committing decoder
should have failed at the device end.

In order to checkout this error as quickly as possible, driver needs
to check the interleave capability of target during attaching it to
region.

Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register),
bits 11 and 12 indicate the capability to establish interleaving in 3, 6,
12 and 16 ways. If these bits are not set, the target cannot be attached to
a region utilizing such interleave ways.

Additionally, bits 8 and 9 represent the capability of the bits used for
interleaving in the address, Linux tracks this in the cxl_port
interleave_mask.

Per CXL specification r3.1(8.2.4.20.13 Decoder Protection):
  eIW means encoded Interleave Ways.
  eIG means encoded Interleave Granularity.

  in HPA:
  if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used,
  the interleave bits are none, the following check is ignored.

  if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW + 8 - 1.

  if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits
  start at bit position eIG + 8 and end at eIG + eIW - 1.

  if the interleave mask is insufficient to cover the required interleave
  bits, the target cannot be attached to the region.

Fixes: 384e624bb2 ("cxl/region: Attach endpoint decoders")
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/20240614084755.59503-2-yaoxt.fnst@fujitsu.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-07-05 09:34:07 +02:00
..
core cxl/region: check interleave capability 2024-07-05 09:34:07 +02:00
Kconfig cxl: fix CONFIG_FW_LOADER dependency 2023-07-14 14:32:22 -06:00
Makefile cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation 2022-11-30 16:30:47 -08:00
acpi.c cxl/acpi: Fix load failures due to single window creation failure 2024-03-01 13:34:59 +01:00
cxl.h cxl/region: check interleave capability 2024-07-05 09:34:07 +02:00
cxlmem.h cxl/region: check interleave capability 2024-07-05 09:34:07 +02:00
cxlpci.h cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
mem.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
pci.c cxl/core/regs: Rename @dev to @host in struct cxl_register_map 2023-11-20 11:59:31 +01:00
pmem.c cxl/mbox: Move mailbox related driver state to its own data structure 2023-06-25 14:31:08 -07:00
pmu.h cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
port.c Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl 2023-06-25 18:56:13 -07:00
security.c Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl 2023-06-25 17:16:51 -07:00