241 lines
6.2 KiB
C
241 lines
6.2 KiB
C
#ifndef _ASM_X86_SPINLOCK_H
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#define _ASM_X86_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <linux/compiler.h>
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#include <asm/paravirt.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* These are fair FIFO ticket locks, which support up to 2^16 CPUs.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#ifdef CONFIG_X86_32
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# define LOCK_PTR_REG "a"
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#else
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# define LOCK_PTR_REG "D"
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#endif
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#if defined(CONFIG_X86_32) && \
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(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
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/*
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* On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
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* (PPro errata 66, 92)
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*/
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# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
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#else
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# define UNLOCK_LOCK_PREFIX
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#endif
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/*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* We use an xadd covering *both* parts of the lock, to increment the tail and
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* also load the position of the head, which takes care of memory ordering
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* issues and should be optimal for the uncontended case. Note the tail must be
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* in the high part, because a wide xadd increment of the low part would carry
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* up and contaminate the high part.
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*/
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static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
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{
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register struct __raw_tickets inc = { .tail = 1 };
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inc = xadd(&lock->tickets, inc);
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for (;;) {
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if (inc.head == inc.tail)
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break;
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cpu_relax();
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inc.head = ACCESS_ONCE(lock->tickets.head);
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}
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barrier(); /* make sure nothing creeps before the lock is taken */
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}
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static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
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{
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arch_spinlock_t old, new;
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old.tickets = ACCESS_ONCE(lock->tickets);
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if (old.tickets.head != old.tickets.tail)
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return 0;
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new.head_tail = old.head_tail + (1 << TICKET_SHIFT);
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/* cmpxchg is a full barrier, so nothing can move before it */
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return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
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}
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static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
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{
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__add(&lock->tickets.head, 1, UNLOCK_LOCK_PREFIX);
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}
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static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
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{
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struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
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return tmp.tail != tmp.head;
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}
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static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
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{
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struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
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return (__ticket_t)(tmp.tail - tmp.head) > 1;
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}
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#ifndef CONFIG_PARAVIRT_SPINLOCKS
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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return __ticket_spin_is_locked(lock);
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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return __ticket_spin_is_contended(lock);
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}
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#define arch_spin_is_contended arch_spin_is_contended
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static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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__ticket_spin_lock(lock);
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}
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static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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return __ticket_spin_trylock(lock);
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}
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static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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__ticket_spin_unlock(lock);
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}
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static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
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unsigned long flags)
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{
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arch_spin_lock(lock);
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}
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#endif /* CONFIG_PARAVIRT_SPINLOCKS */
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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while (arch_spin_is_locked(lock))
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cpu_relax();
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int arch_read_can_lock(arch_rwlock_t *lock)
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{
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return lock->lock > 0;
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}
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int arch_write_can_lock(arch_rwlock_t *lock)
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{
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return lock->write == WRITE_LOCK_CMP;
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}
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
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"jns 1f\n"
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"call __read_lock_failed\n\t"
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"1:\n"
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::LOCK_PTR_REG (rw) : "memory");
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
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"jz 1f\n"
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"call __write_lock_failed\n\t"
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"1:\n"
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::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
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: "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t *lock)
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{
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READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
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if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
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return 1;
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READ_LOCK_ATOMIC(inc)(count);
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return 0;
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}
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static inline int arch_write_trylock(arch_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)&lock->write;
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if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
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return 1;
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atomic_add(WRITE_LOCK_CMP, count);
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return 0;
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
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:"+m" (rw->lock) : : "memory");
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
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: "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
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}
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#undef READ_LOCK_SIZE
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#undef READ_LOCK_ATOMIC
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#undef WRITE_LOCK_ADD
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#undef WRITE_LOCK_SUB
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#undef WRITE_LOCK_CMP
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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/* The {read|write|spin}_lock() on x86 are full memory barriers. */
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static inline void smp_mb__after_lock(void) { }
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#define ARCH_HAS_SMP_MB_AFTER_LOCK
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#endif /* _ASM_X86_SPINLOCK_H */
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