282 lines
10 KiB
C
282 lines
10 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "umc_v6_1.h"
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#include "amdgpu_ras.h"
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#include "amdgpu.h"
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#include "rsmu/rsmu_0_0_2_offset.h"
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#include "rsmu/rsmu_0_0_2_sh_mask.h"
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#include "umc/umc_6_1_1_offset.h"
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#include "umc/umc_6_1_1_sh_mask.h"
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#define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10
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/*
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* (addr / 256) * 8192, the higher 26 bits in ErrorAddr
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* is the index of 8KB block
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*/
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#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
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/* channel index is the index of 256B block */
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#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8)
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/* offset in 256B block */
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#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL)
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const uint32_t
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umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
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{2, 18, 11, 27}, {4, 20, 13, 29},
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{1, 17, 8, 24}, {7, 23, 14, 30},
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{10, 26, 3, 19}, {12, 28, 5, 21},
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{9, 25, 0, 16}, {15, 31, 6, 22}
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};
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static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
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uint32_t umc_instance)
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{
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uint32_t rsmu_umc_index;
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rsmu_umc_index = RREG32_SOC15(RSMU, 0,
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mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 1);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_INSTANCE, umc_instance);
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rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_WREN, 1 << umc_instance);
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WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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rsmu_umc_index);
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}
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static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
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{
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WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 0);
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}
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static uint32_t umc_v6_1_get_umc_inst(struct amdgpu_device *adev)
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{
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uint32_t rsmu_umc_index;
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rsmu_umc_index = RREG32_SOC15(RSMU, 0,
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mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
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return REG_GET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_INSTANCE);
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}
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static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt, ecc_err_cnt_addr;
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
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/* select the lower chip and check the error count */
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ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 0);
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WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
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ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
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UMC_V6_1_CE_CNT_INIT);
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/* clear the lower chip err count */
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WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
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/* select the higher chip and check the err counter */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 1);
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WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
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ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
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UMC_V6_1_CE_CNT_INIT);
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/* clear the higher chip err count */
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WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
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/* check for SRAM correctable error
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MCUMC_STATUS is a 64 bit register */
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mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
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/* check the MCUMC_STATUS */
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mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
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if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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static void umc_v6_1_query_error_count(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint32_t umc_reg_offset,
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uint32_t channel_index)
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{
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umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
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&(err_data->ce_count));
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umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
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&(err_data->ue_count));
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}
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static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_for_each_channel(umc_v6_1_query_error_count);
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}
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static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t umc_reg_offset, uint32_t channel_index)
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{
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uint32_t lsb, mc_umc_status_addr;
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uint64_t mc_umc_status, err_addr, retired_page;
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struct eeprom_table_record *err_rec;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
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/* skip error address process if -ENOMEM */
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if (!err_data->err_addr) {
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/* clear umc status */
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WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
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return;
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}
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err_rec = &err_data->err_addr[err_data->err_addr_cnt];
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mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
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/* calculate error address if ue/ce error is detected */
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
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err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4);
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/* the lowest lsb bits should be ignored */
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lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
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err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
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err_addr &= ~((0x1ULL << lsb) - 1);
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/* translate umc channel address to soc pa, 3 parts are included */
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retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
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ADDR_OF_256B_BLOCK(channel_index) |
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OFFSET_IN_256B_BLOCK(err_addr);
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/* we only save ue error information currently, ce is skipped */
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
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== 1) {
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err_rec->address = err_addr;
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/* page frame address is saved */
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err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
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err_rec->ts = (uint64_t)ktime_get_real_seconds();
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err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
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err_rec->cu = 0;
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err_rec->mem_channel = channel_index;
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err_rec->mcumc_id = umc_v6_1_get_umc_inst(adev);
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err_data->err_addr_cnt++;
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}
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}
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/* clear umc status */
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WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
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}
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static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
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}
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static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t umc_reg_offset, uint32_t channel_index)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt_addr;
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
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/* select the lower chip and check the error count */
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ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 0);
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/* set ce error interrupt type to APIC based interrupt */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrInt, 0x1);
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WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
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/* set error count to initial value */
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WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
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/* select the higher chip and check the err counter */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 1);
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WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
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WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
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}
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static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev)
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{
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void *ras_error_status = NULL;
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amdgpu_umc_for_each_channel(umc_v6_1_err_cnt_init_per_channel);
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}
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const struct amdgpu_umc_funcs umc_v6_1_funcs = {
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.err_cnt_init = umc_v6_1_err_cnt_init,
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.ras_late_init = amdgpu_umc_ras_late_init,
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.query_ras_error_count = umc_v6_1_query_ras_error_count,
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.query_ras_error_address = umc_v6_1_query_ras_error_address,
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.enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
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.disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
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};
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