541 lines
18 KiB
C
541 lines
18 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v7_4.h"
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#include "amdgpu_ras.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "nbio/nbio_7_4_sh_mask.h"
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#include "nbio/nbio_7_4_0_smn.h"
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#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
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#include <uapi/linux/kfd_ioctl.h>
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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/*
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* These are nbio v7_4_1 registers mask. Temporarily define these here since
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* nbio v7_4_1 header is incomplete.
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*/
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
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#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
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#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
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#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
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//BIF_MMSCH1_DOORBELL_RANGE
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#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
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#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
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#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
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#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
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static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
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BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
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}
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static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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else
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amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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}
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static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
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}
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static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index, int doorbell_size)
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{
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u32 reg, doorbell_range;
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if (instance < 2)
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reg = instance +
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
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else
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/*
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* These registers address of SDMA2~7 is not consecutive
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* from SDMA0~1. Need plus 4 dwords offset.
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*
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* BIF_SDMA0_DOORBELL_RANGE: 0x3bc0
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* BIF_SDMA1_DOORBELL_RANGE: 0x3bc4
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* BIF_SDMA2_DOORBELL_RANGE: 0x3bd8
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*/
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reg = instance + 0x4 +
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
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doorbell_range = RREG32(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
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WREG32(reg, doorbell_range);
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}
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static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
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int doorbell_index, int instance)
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{
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u32 reg;
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u32 doorbell_range;
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if (instance)
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reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
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else
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reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
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doorbell_range = RREG32(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range,
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BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
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WREG32(reg, doorbell_range);
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}
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static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
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}
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static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
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}
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static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
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} else
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
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WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
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}
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static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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//TODO: Add support for v7.4
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}
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static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_CNTL2);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnPCIE_CNTL2, data);
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}
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static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_BIF_MGCG */
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data = RREG32_PCIE(smnCPM_CONTROL);
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if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_MGCG;
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/* AMD_CG_SUPPORT_BIF_LS */
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data = RREG32_PCIE(smnPCIE_CNTL2);
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if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_LS;
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}
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static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
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/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
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WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
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}
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static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
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}
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static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
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}
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static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
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}
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static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
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}
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const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
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.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
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.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
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.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
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.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
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.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
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.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
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.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
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.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
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.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
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.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
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.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
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.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
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.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
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.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
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.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
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.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
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.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
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.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
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};
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static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
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{
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uint32_t reg;
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reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
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if (reg & 1)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
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if (reg & 0x80000000)
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
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if (!reg) {
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if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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}
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static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
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{
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}
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static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
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{
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uint32_t bif_doorbell_intr_cntl;
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bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
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if (REG_GET_FIELD(bif_doorbell_intr_cntl,
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BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
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/* driver has to clear the interrupt status when bif ring is disabled */
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bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
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BIF_DOORBELL_INT_CNTL,
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RAS_CNTLR_INTERRUPT_CLEAR, 1);
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WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
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amdgpu_ras_global_ras_isr(adev);
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}
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}
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static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
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{
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uint32_t bif_doorbell_intr_cntl;
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bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
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if (REG_GET_FIELD(bif_doorbell_intr_cntl,
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BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
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/* driver has to clear the interrupt status when bif ring is disabled */
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bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
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BIF_DOORBELL_INT_CNTL,
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RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
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WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
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amdgpu_ras_global_ras_isr(adev);
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}
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}
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static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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/* The ras_controller_irq enablement should be done in psp bl when it
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* tries to enable ras feature. Driver only need to set the correct interrupt
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* vector for bare-metal and sriov use case respectively
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*/
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uint32_t bif_intr_cntl;
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bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
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if (state == AMDGPU_IRQ_STATE_ENABLE) {
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/* set interrupt vector select bit to 0 to select
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* vetcor 1 for bare metal case */
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bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
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BIF_INTR_CNTL,
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RAS_INTR_VEC_SEL, 0);
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WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
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}
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return 0;
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}
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static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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/* By design, the ih cookie for ras_controller_irq should be written
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* to BIFring instead of general iv ring. However, due to known bif ring
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* hw bug, it has to be disabled. There is no chance the process function
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* will be involked. Just left it as a dummy one.
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*/
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return 0;
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}
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static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *src,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
/* The ras_controller_irq enablement should be done in psp bl when it
|
|
* tries to enable ras feature. Driver only need to set the correct interrupt
|
|
* vector for bare-metal and sriov use case respectively
|
|
*/
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|
uint32_t bif_intr_cntl;
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|
|
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bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
|
|
if (state == AMDGPU_IRQ_STATE_ENABLE) {
|
|
/* set interrupt vector select bit to 0 to select
|
|
* vetcor 1 for bare metal case */
|
|
bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
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|
BIF_INTR_CNTL,
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|
RAS_INTR_VEC_SEL, 0);
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WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
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|
}
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|
|
|
return 0;
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|
}
|
|
|
|
static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
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|
struct amdgpu_irq_src *source,
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|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
/* By design, the ih cookie for err_event_athub_irq should be written
|
|
* to BIFring instead of general iv ring. However, due to known bif ring
|
|
* hw bug, it has to be disabled. There is no chance the process function
|
|
* will be involked. Just left it as a dummy one.
|
|
*/
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|
return 0;
|
|
}
|
|
|
|
static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
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.set = nbio_v7_4_set_ras_controller_irq_state,
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.process = nbio_v7_4_process_ras_controller_irq,
|
|
};
|
|
|
|
static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
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|
.set = nbio_v7_4_set_ras_err_event_athub_irq_state,
|
|
.process = nbio_v7_4_process_err_event_athub_irq,
|
|
};
|
|
|
|
static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
/* init the irq funcs */
|
|
adev->nbio.ras_controller_irq.funcs =
|
|
&nbio_v7_4_ras_controller_irq_funcs;
|
|
adev->nbio.ras_controller_irq.num_types = 1;
|
|
|
|
/* register ras controller interrupt */
|
|
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
|
|
NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
|
|
&adev->nbio.ras_controller_irq);
|
|
if (r)
|
|
return r;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
|
|
{
|
|
|
|
int r;
|
|
|
|
/* init the irq funcs */
|
|
adev->nbio.ras_err_event_athub_irq.funcs =
|
|
&nbio_v7_4_ras_err_event_athub_irq_funcs;
|
|
adev->nbio.ras_err_event_athub_irq.num_types = 1;
|
|
|
|
/* register ras err event athub interrupt */
|
|
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
|
|
NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
|
|
&adev->nbio.ras_err_event_athub_irq);
|
|
if (r)
|
|
return r;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
|
|
void *ras_error_status)
|
|
{
|
|
uint32_t global_sts, central_sts, int_eoi;
|
|
uint32_t corr, fatal, non_fatal;
|
|
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
|
|
|
|
global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
|
|
corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
|
|
fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
|
|
non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
|
|
ParityErrNonFatal);
|
|
|
|
if (corr)
|
|
err_data->ce_count++;
|
|
if (fatal)
|
|
err_data->ue_count++;
|
|
|
|
if (corr || fatal || non_fatal) {
|
|
central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
|
|
/* clear error status register */
|
|
WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
|
|
|
|
if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
|
|
BIFL_RasContller_Intr_Recv)) {
|
|
/* clear interrupt status register */
|
|
WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
|
|
int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
|
|
int_eoi = REG_SET_FIELD(int_eoi,
|
|
IOHC_INTERRUPT_EOI, SMI_EOI, 1);
|
|
WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
|
|
DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
|
|
}
|
|
|
|
const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
|
|
.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
|
|
.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
|
|
.get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
|
|
.get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
|
|
.get_rev_id = nbio_v7_4_get_rev_id,
|
|
.mc_access_enable = nbio_v7_4_mc_access_enable,
|
|
.hdp_flush = nbio_v7_4_hdp_flush,
|
|
.get_memsize = nbio_v7_4_get_memsize,
|
|
.sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
|
|
.vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
|
|
.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
|
|
.enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
|
|
.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
|
|
.enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
|
|
.update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
|
|
.update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
|
|
.get_clockgating_state = nbio_v7_4_get_clockgating_state,
|
|
.ih_control = nbio_v7_4_ih_control,
|
|
.init_registers = nbio_v7_4_init_registers,
|
|
.detect_hw_virt = nbio_v7_4_detect_hw_virt,
|
|
.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
|
|
.handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
|
|
.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
|
|
.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
|
|
.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
|
|
.query_ras_error_count = nbio_v7_4_query_ras_error_count,
|
|
.ras_late_init = amdgpu_nbio_ras_late_init,
|
|
};
|