102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_MES_H__
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#define __AMDGPU_MES_H__
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struct amdgpu_mes_funcs;
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struct amdgpu_mes {
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struct amdgpu_adev *adev;
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const struct firmware *fw;
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/* mes ucode */
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struct amdgpu_bo *ucode_fw_obj;
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uint64_t ucode_fw_gpu_addr;
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uint32_t *ucode_fw_ptr;
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uint32_t ucode_fw_version;
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uint64_t uc_start_addr;
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/* mes ucode data */
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struct amdgpu_bo *data_fw_obj;
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uint64_t data_fw_gpu_addr;
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uint32_t *data_fw_ptr;
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uint32_t data_fw_version;
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uint64_t data_start_addr;
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/* ip specific functions */
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struct amdgpu_mes_funcs *funcs;
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};
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struct mes_add_queue_input {
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uint32_t process_id;
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uint64_t page_table_base_addr;
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uint64_t process_va_start;
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uint64_t process_va_end;
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uint64_t process_quantum;
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uint64_t process_context_addr;
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uint64_t gang_quantum;
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uint64_t gang_context_addr;
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uint32_t inprocess_gang_priority;
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uint32_t gang_global_priority_level;
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uint32_t doorbell_offset;
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uint64_t mqd_addr;
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uint64_t wptr_addr;
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uint32_t queue_type;
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uint32_t paging;
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};
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struct mes_remove_queue_input {
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uint32_t doorbell_offset;
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uint64_t gang_context_addr;
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};
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struct mes_suspend_gang_input {
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bool suspend_all_gangs;
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uint64_t gang_context_addr;
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uint64_t suspend_fence_addr;
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uint32_t suspend_fence_value;
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};
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struct mes_resume_gang_input {
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bool resume_all_gangs;
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uint64_t gang_context_addr;
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};
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struct amdgpu_mes_funcs {
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int (*add_hw_queue)(struct amdgpu_mes *mes,
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struct mes_add_queue_input *input);
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int (*remove_hw_queue)(struct amdgpu_mes *mes,
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struct mes_remove_queue_input *input);
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int (*suspend_gang)(struct amdgpu_mes *mes,
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struct mes_suspend_gang_input *input);
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int (*resume_gang)(struct amdgpu_mes *mes,
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struct mes_resume_gang_input *input);
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};
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#endif /* __AMDGPU_MES_H__ */
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