342 lines
7.7 KiB
C
342 lines
7.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
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*/
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/*
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* SGI TIOCA AGPGART routines.
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*
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*/
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/io.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/tioca_provider.h>
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#include "agp.h"
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extern int agp_memory_reserved;
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extern uint32_t tioca_gart_found;
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extern struct list_head tioca_list;
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static struct agp_bridge_data **sgi_tioca_agp_bridges;
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/*
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* The aperature size and related information is set up at TIOCA init time.
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* Values for this table will be extracted and filled in at
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* sgi_tioca_fetch_size() time.
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*/
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static struct aper_size_info_fixed sgi_tioca_sizes[] = {
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{0, 0, 0},
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};
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static void *sgi_tioca_alloc_page(struct agp_bridge_data *bridge)
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{
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struct page *page;
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int nid;
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struct tioca_kernel *info =
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(struct tioca_kernel *)bridge->dev_private_data;
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nid = info->ca_closest_node;
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page = alloc_pages_node(nid, GFP_KERNEL, 0);
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if (page == NULL) {
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return 0;
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}
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get_page(page);
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SetPageLocked(page);
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atomic_inc(&agp_bridge->current_memory_agp);
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return page_address(page);
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}
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/*
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* Flush GART tlb's. Cannot selectively flush based on memory so the mem
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* arg is ignored.
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*/
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static void sgi_tioca_tlbflush(struct agp_memory *mem)
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{
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tioca_tlbflush(mem->bridge->dev_private_data);
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}
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/*
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* Given an address of a host physical page, turn it into a valid gart
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* entry.
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*/
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static unsigned long
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sgi_tioca_mask_memory(struct agp_bridge_data *bridge,
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unsigned long addr, int type)
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{
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return tioca_physpage_to_gart(addr);
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}
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static void sgi_tioca_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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tioca_fastwrite_enable(bridge->dev_private_data);
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}
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/*
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* sgi_tioca_configure() doesn't have anything to do since the base CA driver
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* has alreay set up the GART.
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*/
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static int sgi_tioca_configure(void)
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{
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return 0;
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}
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/*
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* Determine gfx aperature size. This has already been determined by the
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* CA driver init, so just need to set agp_bridge values accordingly.
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*/
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static int sgi_tioca_fetch_size(void)
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{
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struct tioca_kernel *info =
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(struct tioca_kernel *)agp_bridge->dev_private_data;
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sgi_tioca_sizes[0].size = info->ca_gfxap_size / MB(1);
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sgi_tioca_sizes[0].num_entries = info->ca_gfxgart_entries;
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return sgi_tioca_sizes[0].size;
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}
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static int sgi_tioca_create_gatt_table(struct agp_bridge_data *bridge)
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{
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struct tioca_kernel *info =
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(struct tioca_kernel *)bridge->dev_private_data;
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bridge->gatt_table_real = (u32 *) info->ca_gfxgart;
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bridge->gatt_table = bridge->gatt_table_real;
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bridge->gatt_bus_addr = info->ca_gfxgart_base;
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return 0;
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}
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static int sgi_tioca_free_gatt_table(struct agp_bridge_data *bridge)
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{
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return 0;
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}
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static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int num_entries;
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size_t i;
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off_t j;
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void *temp;
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struct agp_bridge_data *bridge;
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u64 *table;
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bridge = mem->bridge;
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if (!bridge)
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return -EINVAL;
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table = (u64 *)bridge->gatt_table;
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temp = bridge->current_size;
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switch (bridge->driver->size_type) {
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case U8_APER_SIZE:
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num_entries = A_SIZE_8(temp)->num_entries;
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break;
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case U16_APER_SIZE:
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num_entries = A_SIZE_16(temp)->num_entries;
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break;
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case U32_APER_SIZE:
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num_entries = A_SIZE_32(temp)->num_entries;
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break;
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case FIXED_APER_SIZE:
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num_entries = A_SIZE_FIX(temp)->num_entries;
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break;
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case LVL2_APER_SIZE:
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return -EINVAL;
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break;
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default:
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num_entries = 0;
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break;
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}
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num_entries -= agp_memory_reserved / PAGE_SIZE;
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if (num_entries < 0)
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num_entries = 0;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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j = pg_start;
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while (j < (pg_start + mem->page_count)) {
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if (table[j])
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return -EBUSY;
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j++;
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}
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if (mem->is_flushed == FALSE) {
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bridge->driver->cache_flush();
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mem->is_flushed = TRUE;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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table[j] =
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bridge->driver->mask_memory(bridge, mem->memory[i],
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mem->type);
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}
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bridge->driver->tlb_flush(mem);
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return 0;
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}
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static int sgi_tioca_remove_memory(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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size_t i;
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struct agp_bridge_data *bridge;
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u64 *table;
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bridge = mem->bridge;
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if (!bridge)
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return -EINVAL;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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table = (u64 *)bridge->gatt_table;
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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table[i] = 0;
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}
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bridge->driver->tlb_flush(mem);
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return 0;
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}
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static void sgi_tioca_cache_flush(void)
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{
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}
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/*
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* Cleanup. Nothing to do as the CA driver owns the GART.
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*/
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static void sgi_tioca_cleanup(void)
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{
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}
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static struct agp_bridge_data *sgi_tioca_find_bridge(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge;
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list_for_each_entry(bridge, &agp_bridges, list) {
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if (bridge->dev->bus == pdev->bus)
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break;
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}
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return bridge;
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}
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const struct agp_bridge_driver sgi_tioca_driver = {
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.owner = THIS_MODULE,
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.size_type = U16_APER_SIZE,
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.configure = sgi_tioca_configure,
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.fetch_size = sgi_tioca_fetch_size,
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.cleanup = sgi_tioca_cleanup,
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.tlb_flush = sgi_tioca_tlbflush,
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.mask_memory = sgi_tioca_mask_memory,
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.agp_enable = sgi_tioca_agp_enable,
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.cache_flush = sgi_tioca_cache_flush,
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.create_gatt_table = sgi_tioca_create_gatt_table,
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.free_gatt_table = sgi_tioca_free_gatt_table,
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.insert_memory = sgi_tioca_insert_memory,
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.remove_memory = sgi_tioca_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = sgi_tioca_alloc_page,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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.cant_use_aperture = 1,
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.needs_scratch_page = 0,
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.num_aperture_sizes = 1,
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};
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static int __devinit agp_sgi_init(void)
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{
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unsigned int j;
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struct tioca_kernel *info;
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struct pci_dev *pdev = NULL;
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if (tioca_gart_found)
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printk(KERN_INFO PFX "SGI TIO CA GART driver initialized.\n");
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else
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return 0;
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sgi_tioca_agp_bridges = kmalloc(tioca_gart_found *
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sizeof(struct agp_bridge_data *),
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GFP_KERNEL);
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if (!sgi_tioca_agp_bridges)
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return -ENOMEM;
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j = 0;
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list_for_each_entry(info, &tioca_list, ca_list) {
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struct list_head *tmp;
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if (list_empty(info->ca_devices))
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continue;
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list_for_each(tmp, info->ca_devices) {
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u8 cap_ptr;
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pdev = pci_dev_b(tmp);
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if (pdev->class != (PCI_CLASS_DISPLAY_VGA << 8))
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continue;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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continue;
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}
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sgi_tioca_agp_bridges[j] = agp_alloc_bridge();
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printk(KERN_INFO PFX "bridge %d = 0x%p\n", j,
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sgi_tioca_agp_bridges[j]);
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if (sgi_tioca_agp_bridges[j]) {
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sgi_tioca_agp_bridges[j]->dev = pdev;
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sgi_tioca_agp_bridges[j]->dev_private_data = info;
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sgi_tioca_agp_bridges[j]->driver = &sgi_tioca_driver;
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sgi_tioca_agp_bridges[j]->gart_bus_addr =
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info->ca_gfxap_base;
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sgi_tioca_agp_bridges[j]->mode = (0x7D << 24) | /* 126 requests */
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(0x1 << 9) | /* SBA supported */
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(0x1 << 5) | /* 64-bit addresses supported */
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(0x1 << 4) | /* FW supported */
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(0x1 << 3) | /* AGP 3.0 mode */
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0x2; /* 8x transfer only */
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sgi_tioca_agp_bridges[j]->current_size =
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sgi_tioca_agp_bridges[j]->previous_size =
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(void *)&sgi_tioca_sizes[0];
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agp_add_bridge(sgi_tioca_agp_bridges[j]);
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}
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j++;
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}
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agp_find_bridge = &sgi_tioca_find_bridge;
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return 0;
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}
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static void __devexit agp_sgi_cleanup(void)
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{
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kfree(sgi_tioca_agp_bridges);
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sgi_tioca_agp_bridges = NULL;
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}
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module_init(agp_sgi_init);
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module_exit(agp_sgi_cleanup);
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MODULE_LICENSE("GPL and additional rights");
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