442 lines
14 KiB
C
442 lines
14 KiB
C
#ifndef _MXSER_H
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#define _MXSER_H
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/*
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* Semi-public control interfaces
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*/
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/*
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* MOXA ioctls
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*/
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#define MOXA 0x400
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#define MOXA_GETDATACOUNT (MOXA + 23)
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#define MOXA_GET_CONF (MOXA + 35)
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#define MOXA_DIAGNOSE (MOXA + 50)
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#define MOXA_CHKPORTENABLE (MOXA + 60)
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#define MOXA_HighSpeedOn (MOXA + 61)
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#define MOXA_GET_MAJOR (MOXA + 63)
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#define MOXA_GET_CUMAJOR (MOXA + 64)
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#define MOXA_GETMSTATUS (MOXA + 65)
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#define MOXA_SET_OP_MODE (MOXA + 66)
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#define MOXA_GET_OP_MODE (MOXA + 67)
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#define RS232_MODE 0
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#define RS485_2WIRE_MODE 1
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#define RS422_MODE 2
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#define RS485_4WIRE_MODE 3
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#define OP_MODE_MASK 3
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// above add by Victor Yu. 01-05-2004
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#define TTY_THRESHOLD_THROTTLE 128
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#define HI_WATER 768
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// added by James. 03-11-2004.
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#define MOXA_SDS_GETICOUNTER (MOXA + 68)
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#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
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// (above) added by James.
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#define MOXA_ASPP_OQUEUE (MOXA + 70)
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#define MOXA_ASPP_SETBAUD (MOXA + 71)
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#define MOXA_ASPP_GETBAUD (MOXA + 72)
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#define MOXA_ASPP_MON (MOXA + 73)
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#define MOXA_ASPP_LSTATUS (MOXA + 74)
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#define MOXA_ASPP_MON_EXT (MOXA + 75)
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#define MOXA_SET_BAUD_METHOD (MOXA + 76)
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/* --------------------------------------------------- */
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#define NPPI_NOTIFY_PARITY 0x01
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#define NPPI_NOTIFY_FRAMING 0x02
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#define NPPI_NOTIFY_HW_OVERRUN 0x04
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#define NPPI_NOTIFY_SW_OVERRUN 0x08
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#define NPPI_NOTIFY_BREAK 0x10
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#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low
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#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low
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#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received
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#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent
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//CheckIsMoxaMust return value
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#define MOXA_OTHER_UART 0x00
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#define MOXA_MUST_MU150_HWID 0x01
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#define MOXA_MUST_MU860_HWID 0x02
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// follow just for Moxa Must chip define.
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//
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// when LCR register (offset 0x03) write following value,
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// the Must chip will enter enchance mode. And write value
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// on EFR (offset 0x02) bit 6,7 to change bank.
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#define MOXA_MUST_ENTER_ENCHANCE 0xBF
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// when enhance mode enable, access on general bank register
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#define MOXA_MUST_GDL_REGISTER 0x07
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#define MOXA_MUST_GDL_MASK 0x7F
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#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
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#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO
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// enchance register bank select and enchance mode setting register
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// when LCR register equal to 0xBF
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#define MOXA_MUST_EFR_REGISTER 0x02
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// enchance mode enable
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#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
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// enchance reister bank set 0, 1, 2
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#define MOXA_MUST_EFR_BANK0 0x00
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#define MOXA_MUST_EFR_BANK1 0x40
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#define MOXA_MUST_EFR_BANK2 0x80
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#define MOXA_MUST_EFR_BANK3 0xC0
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#define MOXA_MUST_EFR_BANK_MASK 0xC0
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// set XON1 value register, when LCR=0xBF and change to bank0
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#define MOXA_MUST_XON1_REGISTER 0x04
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// set XON2 value register, when LCR=0xBF and change to bank0
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#define MOXA_MUST_XON2_REGISTER 0x05
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// set XOFF1 value register, when LCR=0xBF and change to bank0
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#define MOXA_MUST_XOFF1_REGISTER 0x06
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// set XOFF2 value register, when LCR=0xBF and change to bank0
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#define MOXA_MUST_XOFF2_REGISTER 0x07
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#define MOXA_MUST_RBRTL_REGISTER 0x04
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#define MOXA_MUST_RBRTH_REGISTER 0x05
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#define MOXA_MUST_RBRTI_REGISTER 0x06
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#define MOXA_MUST_THRTL_REGISTER 0x07
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#define MOXA_MUST_ENUM_REGISTER 0x04
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#define MOXA_MUST_HWID_REGISTER 0x05
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#define MOXA_MUST_ECR_REGISTER 0x06
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#define MOXA_MUST_CSR_REGISTER 0x07
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// good data mode enable
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#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
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// only good data put into RxFIFO
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#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
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// enable CTS interrupt
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#define MOXA_MUST_IER_ECTSI 0x80
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// enable RTS interrupt
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#define MOXA_MUST_IER_ERTSI 0x40
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// enable Xon/Xoff interrupt
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#define MOXA_MUST_IER_XINT 0x20
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// enable GDA interrupt
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#define MOXA_MUST_IER_EGDAI 0x10
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#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
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// GDA interrupt pending
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#define MOXA_MUST_IIR_GDA 0x1C
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#define MOXA_MUST_IIR_RDA 0x04
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#define MOXA_MUST_IIR_RTO 0x0C
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#define MOXA_MUST_IIR_LSR 0x06
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// recieved Xon/Xoff or specical interrupt pending
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#define MOXA_MUST_IIR_XSC 0x10
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// RTS/CTS change state interrupt pending
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#define MOXA_MUST_IIR_RTSCTS 0x20
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#define MOXA_MUST_IIR_MASK 0x3E
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#define MOXA_MUST_MCR_XON_FLAG 0x40
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#define MOXA_MUST_MCR_XON_ANY 0x80
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#define MOXA_MUST_MCR_TX_XON 0x08
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// software flow control on chip mask value
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#define MOXA_MUST_EFR_SF_MASK 0x0F
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// send Xon1/Xoff1
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#define MOXA_MUST_EFR_SF_TX1 0x08
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// send Xon2/Xoff2
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#define MOXA_MUST_EFR_SF_TX2 0x04
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// send Xon1,Xon2/Xoff1,Xoff2
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#define MOXA_MUST_EFR_SF_TX12 0x0C
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// don't send Xon/Xoff
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#define MOXA_MUST_EFR_SF_TX_NO 0x00
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// Tx software flow control mask
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#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
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// don't receive Xon/Xoff
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#define MOXA_MUST_EFR_SF_RX_NO 0x00
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// receive Xon1/Xoff1
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#define MOXA_MUST_EFR_SF_RX1 0x02
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// receive Xon2/Xoff2
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#define MOXA_MUST_EFR_SF_RX2 0x01
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// receive Xon1,Xon2/Xoff1,Xoff2
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#define MOXA_MUST_EFR_SF_RX12 0x03
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// Rx software flow control mask
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#define MOXA_MUST_EFR_SF_RX_MASK 0x03
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//#define MOXA_MUST_MIN_XOFFLIMIT 66
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//#define MOXA_MUST_MIN_XONLIMIT 20
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//#define ID1_RX_TRIG 120
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#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
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if ( (info)->IsMoxaMustChipFlag && \
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(info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
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(info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
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(info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
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} \
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}
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#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK0; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK0; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK0; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK0; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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//#define MOXA_MUST_RBRL_VALUE 4
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#define SET_MOXA_MUST_FIFO_VALUE(info) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((info)->base+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \
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__efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK1; \
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outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \
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outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \
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outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \
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outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \
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outb(__oldlcr, (info)->base+UART_LCR); \
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}
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#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK2; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_BANK_MASK; \
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__efr |= MOXA_MUST_EFR_BANK2; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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*pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_MASK; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_MASK; \
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__efr |= MOXA_MUST_EFR_SF_TX1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
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__efr |= MOXA_MUST_EFR_SF_TX1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_MASK; \
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__efr |= MOXA_MUST_EFR_SF_RX1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
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__efr |= MOXA_MUST_EFR_SF_RX1; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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}
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#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
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u8 __oldlcr, __efr; \
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__oldlcr = inb((baseio)+UART_LCR); \
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|
outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
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__efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
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__efr &= ~MOXA_MUST_EFR_SF_MASK; \
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__efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \
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outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
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outb(__oldlcr, (baseio)+UART_LCR); \
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|
}
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|
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#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
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|
u8 __oldmcr; \
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|
__oldmcr = inb((baseio)+UART_MCR); \
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|
__oldmcr |= MOXA_MUST_MCR_XON_ANY; \
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|
outb(__oldmcr, (baseio)+UART_MCR); \
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|
}
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|
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|
#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
|
|
u8 __oldmcr; \
|
|
__oldmcr = inb((baseio)+UART_MCR); \
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|
__oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
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|
outb(__oldmcr, (baseio)+UART_MCR); \
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|
}
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|
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#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
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|
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#endif
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