251 lines
6.1 KiB
C
251 lines
6.1 KiB
C
/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Flat APIC subarch code.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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#include <linux/errno.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/hardirq.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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#include <asm/genapic.h>
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#include <mach_apicdef.h>
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#ifdef CONFIG_ACPI
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#include <acpi/acpi_bus.h>
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#endif
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static int __init flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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return 1;
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}
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static cpumask_t flat_target_cpus(void)
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{
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return cpu_online_map;
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}
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static cpumask_t flat_vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static void flat_init_apic_ldr(void)
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{
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unsigned long val;
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unsigned long num, id;
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num = smp_processor_id();
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id = 1UL << num;
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apic_write(APIC_DFR, APIC_DFR_FLAT);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write(APIC_LDR, val);
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}
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static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
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{
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unsigned long mask = cpus_addr(cpumask)[0];
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unsigned long flags;
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local_irq_save(flags);
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__send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL);
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local_irq_restore(flags);
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}
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static void flat_send_IPI_allbutself(int vector)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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int hotplug = 1;
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#else
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int hotplug = 0;
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#endif
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if (hotplug || vector == NMI_VECTOR) {
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cpumask_t allbutme = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutme);
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if (!cpus_empty(allbutme))
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flat_send_IPI_mask(allbutme, vector);
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} else if (num_online_cpus() > 1) {
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__send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
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}
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}
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static void flat_send_IPI_all(int vector)
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{
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if (vector == NMI_VECTOR)
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flat_send_IPI_mask(cpu_online_map, vector);
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else
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__send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
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}
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned int id;
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id = (((x)>>24) & 0xFFu);
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = ((id & 0xFFu)<<24);
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return x;
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}
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static unsigned int read_xapic_id(void)
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{
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unsigned int id;
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id = get_apic_id(apic_read(APIC_ID));
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return id;
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}
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static int flat_apic_id_registered(void)
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{
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return physid_isset(read_xapic_id(), phys_cpu_present_map);
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}
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static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
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}
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static unsigned int phys_pkg_id(int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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struct genapic apic_flat = {
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.name = "flat",
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.acpi_madt_oem_check = flat_acpi_madt_oem_check,
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.int_delivery_mode = dest_LowestPrio,
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.int_dest_mode = (APIC_DEST_LOGICAL != 0),
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.target_cpus = flat_target_cpus,
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.vector_allocation_domain = flat_vector_allocation_domain,
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.apic_id_registered = flat_apic_id_registered,
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.init_apic_ldr = flat_init_apic_ldr,
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.send_IPI_all = flat_send_IPI_all,
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.send_IPI_allbutself = flat_send_IPI_allbutself,
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.send_IPI_mask = flat_send_IPI_mask,
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.send_IPI_self = apic_send_IPI_self,
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.cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = (0xFFu<<24),
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};
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/*
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* Physflat mode is used when there are more than 8 CPUs on a AMD system.
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* We cannot use logical delivery in this case because the mask
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* overflows, so use physical mode.
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*/
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static int __init physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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#ifdef CONFIG_ACPI
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/*
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* Quirk: some x86_64 machines can only use physical APIC mode
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* regardless of how many processors are present (x86_64 ES7000
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* is an example).
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*/
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if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
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(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL))
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return 1;
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#endif
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return 0;
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}
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static cpumask_t physflat_target_cpus(void)
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{
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return cpu_online_map;
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}
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static cpumask_t physflat_vector_allocation_domain(int cpu)
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{
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return cpumask_of_cpu(cpu);
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}
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static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
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{
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send_IPI_mask_sequence(cpumask, vector);
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}
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static void physflat_send_IPI_allbutself(int vector)
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{
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cpumask_t allbutme = cpu_online_map;
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cpu_clear(smp_processor_id(), allbutme);
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physflat_send_IPI_mask(allbutme, vector);
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}
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static void physflat_send_IPI_all(int vector)
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{
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physflat_send_IPI_mask(cpu_online_map, vector);
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}
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static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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struct genapic apic_physflat = {
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.name = "physical flat",
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.acpi_madt_oem_check = physflat_acpi_madt_oem_check,
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = physflat_target_cpus,
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.vector_allocation_domain = physflat_vector_allocation_domain,
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.apic_id_registered = flat_apic_id_registered,
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.init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
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.send_IPI_all = physflat_send_IPI_all,
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.send_IPI_allbutself = physflat_send_IPI_allbutself,
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.send_IPI_mask = physflat_send_IPI_mask,
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.send_IPI_self = apic_send_IPI_self,
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.cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = (0xFFu<<24),
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};
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