1064 lines
26 KiB
C
1064 lines
26 KiB
C
/*
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* drivers/net/phy/marvell.c
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*
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* Driver for Marvell PHYs
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*
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* Author: Andy Fleming
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc.
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*
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* Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/marvell_phy.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <linux/uaccess.h>
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#define MII_MARVELL_PHY_PAGE 22
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#define MII_M1011_IEVENT 0x13
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#define MII_M1011_IEVENT_CLEAR 0x0000
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#define MII_M1011_IMASK 0x12
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#define MII_M1011_IMASK_INIT 0x6400
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#define MII_M1011_IMASK_CLEAR 0x0000
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#define MII_M1011_PHY_SCR 0x10
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#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
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#define MII_M1145_PHY_EXT_CR 0x14
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#define MII_M1145_RGMII_RX_DELAY 0x0080
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#define MII_M1145_RGMII_TX_DELAY 0x0002
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#define MII_M1111_PHY_LED_CONTROL 0x18
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#define MII_M1111_PHY_LED_DIRECT 0x4100
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#define MII_M1111_PHY_LED_COMBINE 0x411c
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#define MII_M1111_PHY_EXT_CR 0x14
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#define MII_M1111_RX_DELAY 0x80
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#define MII_M1111_TX_DELAY 0x2
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#define MII_M1111_PHY_EXT_SR 0x1b
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#define MII_M1111_HWCFG_MODE_MASK 0xf
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#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
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#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
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#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
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#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
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#define MII_M1111_COPPER 0
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#define MII_M1111_FIBER 1
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#define MII_88E1121_PHY_MSCR_PAGE 2
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#define MII_88E1121_PHY_MSCR_REG 21
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#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
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#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
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#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
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#define MII_88E1318S_PHY_MSCR1_REG 16
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#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
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/* Copper Specific Interrupt Enable Register */
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#define MII_88E1318S_PHY_CSIER 0x12
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/* WOL Event Interrupt Enable */
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#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
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/* LED Timer Control Register */
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#define MII_88E1318S_PHY_LED_PAGE 0x03
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#define MII_88E1318S_PHY_LED_TCR 0x12
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#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
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#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
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#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
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/* Magic Packet MAC address registers */
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
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#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
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#define MII_88E1318S_PHY_WOL_PAGE 0x11
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#define MII_88E1318S_PHY_WOL_CTRL 0x10
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#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
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#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
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#define MII_88E1121_PHY_LED_CTRL 16
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#define MII_88E1121_PHY_LED_PAGE 3
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#define MII_88E1121_PHY_LED_DEF 0x0030
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#define MII_M1011_PHY_STATUS 0x11
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#define MII_M1011_PHY_STATUS_1000 0x8000
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#define MII_M1011_PHY_STATUS_100 0x4000
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#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
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#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
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#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_STATUS_LINK 0x0400
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#define MII_M1116R_CONTROL_REG_MAC 21
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MODULE_DESCRIPTION("Marvell PHY driver");
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MODULE_AUTHOR("Andy Fleming");
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MODULE_LICENSE("GPL");
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static int marvell_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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/* Clear the interrupts by reading the reg */
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err = phy_read(phydev, MII_M1011_IEVENT);
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if (err < 0)
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return err;
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return 0;
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}
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static int marvell_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
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else
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err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
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return err;
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}
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static int marvell_config_aneg(struct phy_device *phydev)
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{
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int err;
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/* The Marvell PHY has an errata which requires
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* that certain registers get written in order
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* to restart autonegotiation */
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (err < 0)
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return err;
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err = phy_write(phydev, 0x1d, 0x1f);
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if (err < 0)
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return err;
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err = phy_write(phydev, 0x1e, 0x200c);
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if (err < 0)
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return err;
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err = phy_write(phydev, 0x1d, 0x5);
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if (err < 0)
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return err;
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err = phy_write(phydev, 0x1e, 0);
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if (err < 0)
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return err;
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err = phy_write(phydev, 0x1e, 0x100);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_M1011_PHY_SCR,
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MII_M1011_PHY_SCR_AUTO_CROSS);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
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MII_M1111_PHY_LED_DIRECT);
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if (err < 0)
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return err;
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err = genphy_config_aneg(phydev);
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if (err < 0)
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return err;
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if (phydev->autoneg != AUTONEG_ENABLE) {
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int bmcr;
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/*
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* A write to speed/duplex bits (that is performed by
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* genphy_config_aneg() call above) must be followed by
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* a software reset. Otherwise, the write has no effect.
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*/
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
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if (err < 0)
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return err;
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}
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return 0;
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}
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#ifdef CONFIG_OF_MDIO
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/*
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* Set and/or override some configuration registers based on the
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* marvell,reg-init property stored in the of_node for the phydev.
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*
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* marvell,reg-init = <reg-page reg mask value>,...;
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*
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* There may be one or more sets of <reg-page reg mask value>:
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*
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* reg-page: which register bank to use.
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* reg: the register.
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* mask: if non-zero, ANDed with existing register value.
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* value: ORed with the masked value and written to the regiser.
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*
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*/
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static int marvell_of_reg_init(struct phy_device *phydev)
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{
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const __be32 *paddr;
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int len, i, saved_page, current_page, page_changed, ret;
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if (!phydev->dev.of_node)
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return 0;
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paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
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if (!paddr || len < (4 * sizeof(*paddr)))
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return 0;
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saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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if (saved_page < 0)
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return saved_page;
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page_changed = 0;
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current_page = saved_page;
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ret = 0;
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len /= sizeof(*paddr);
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for (i = 0; i < len - 3; i += 4) {
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u16 reg_page = be32_to_cpup(paddr + i);
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u16 reg = be32_to_cpup(paddr + i + 1);
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u16 mask = be32_to_cpup(paddr + i + 2);
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u16 val_bits = be32_to_cpup(paddr + i + 3);
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int val;
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if (reg_page != current_page) {
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current_page = reg_page;
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page_changed = 1;
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ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
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if (ret < 0)
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goto err;
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}
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val = 0;
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if (mask) {
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val = phy_read(phydev, reg);
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if (val < 0) {
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ret = val;
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goto err;
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}
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val &= mask;
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}
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val |= val_bits;
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ret = phy_write(phydev, reg, val);
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if (ret < 0)
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goto err;
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}
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err:
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if (page_changed) {
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i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
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if (ret == 0)
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ret = i;
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}
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return ret;
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}
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#else
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static int marvell_of_reg_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int m88e1121_config_aneg(struct phy_device *phydev)
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{
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int err, oldpage, mscr;
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
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MII_88E1121_PHY_MSCR_PAGE);
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if (err < 0)
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return err;
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
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MII_88E1121_PHY_MSCR_DELAY_MASK;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
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MII_88E1121_PHY_MSCR_TX_DELAY);
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
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else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
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err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
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if (err < 0)
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return err;
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}
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phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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err = phy_write(phydev, MII_BMCR, BMCR_RESET);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_M1011_PHY_SCR,
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MII_M1011_PHY_SCR_AUTO_CROSS);
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if (err < 0)
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return err;
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
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phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
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phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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err = genphy_config_aneg(phydev);
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return err;
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}
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static int m88e1318_config_aneg(struct phy_device *phydev)
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{
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int err, oldpage, mscr;
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oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
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MII_88E1121_PHY_MSCR_PAGE);
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if (err < 0)
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return err;
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mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
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mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
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err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
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if (err < 0)
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return err;
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return m88e1121_config_aneg(phydev);
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}
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static int m88e1510_config_aneg(struct phy_device *phydev)
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{
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int err;
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err = m88e1318_config_aneg(phydev);
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if (err < 0)
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return err;
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return marvell_of_reg_init(phydev);
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}
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static int m88e1116r_config_init(struct phy_device *phydev)
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{
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int temp;
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int err;
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temp = phy_read(phydev, MII_BMCR);
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temp |= BMCR_RESET;
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err = phy_write(phydev, MII_BMCR, temp);
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if (err < 0)
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return err;
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mdelay(500);
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
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if (err < 0)
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return err;
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temp = phy_read(phydev, MII_M1011_PHY_SCR);
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temp |= (7 << 12); /* max number of gigabit attempts */
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temp |= (1 << 11); /* enable downshift */
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temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
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err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
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if (err < 0)
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return err;
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temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
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temp |= (1 << 5);
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temp |= (1 << 4);
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err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
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if (err < 0)
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return err;
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temp = phy_read(phydev, MII_BMCR);
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temp |= BMCR_RESET;
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err = phy_write(phydev, MII_BMCR, temp);
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if (err < 0)
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return err;
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mdelay(500);
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return 0;
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}
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static int m88e1111_config_init(struct phy_device *phydev)
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{
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int err;
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int temp;
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
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if (temp < 0)
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return temp;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
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} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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temp &= ~MII_M1111_TX_DELAY;
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temp |= MII_M1111_RX_DELAY;
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} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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temp &= ~MII_M1111_RX_DELAY;
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temp |= MII_M1111_TX_DELAY;
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}
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err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
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if (err < 0)
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return err;
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temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
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if (temp < 0)
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return temp;
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temp &= ~(MII_M1111_HWCFG_MODE_MASK);
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if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
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temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
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else
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temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
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|
|
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
|
|
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
|
if (temp < 0)
|
|
return temp;
|
|
|
|
temp &= ~(MII_M1111_HWCFG_MODE_MASK);
|
|
temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
|
|
temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
|
|
|
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
|
|
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
|
|
if (temp < 0)
|
|
return temp;
|
|
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
|
|
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
|
if (temp < 0)
|
|
return temp;
|
|
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
|
|
temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
|
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* soft reset */
|
|
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
if (err < 0)
|
|
return err;
|
|
do
|
|
temp = phy_read(phydev, MII_BMCR);
|
|
while (temp & BMCR_RESET);
|
|
|
|
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
|
|
if (temp < 0)
|
|
return temp;
|
|
temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
|
|
temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
|
|
err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
err = marvell_of_reg_init(phydev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
}
|
|
|
|
static int m88e1118_config_aneg(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
|
|
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, MII_M1011_PHY_SCR,
|
|
MII_M1011_PHY_SCR_AUTO_CROSS);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = genphy_config_aneg(phydev);
|
|
return 0;
|
|
}
|
|
|
|
static int m88e1118_config_init(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
|
|
/* Change address */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Enable 1000 Mbit */
|
|
err = phy_write(phydev, 0x15, 0x1070);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Change address */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Adjust LED Control */
|
|
if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
|
|
err = phy_write(phydev, 0x10, 0x1100);
|
|
else
|
|
err = phy_write(phydev, 0x10, 0x021e);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = marvell_of_reg_init(phydev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Reset address */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
}
|
|
|
|
static int m88e1149_config_init(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
|
|
/* Change address */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Enable 1000 Mbit */
|
|
err = phy_write(phydev, 0x15, 0x1048);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = marvell_of_reg_init(phydev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Reset address */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
}
|
|
|
|
static int m88e1145_config_init(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
|
|
/* Take care of errata E0 & E1 */
|
|
err = phy_write(phydev, 0x1d, 0x001b);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, 0x1e, 0x418f);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, 0x1d, 0x0016);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, 0x1e, 0xa2da);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
|
|
int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
|
|
if (temp < 0)
|
|
return temp;
|
|
|
|
temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
|
|
|
|
err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
|
|
err = phy_write(phydev, 0x1d, 0x0012);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
temp = phy_read(phydev, 0x1e);
|
|
if (temp < 0)
|
|
return temp;
|
|
|
|
temp &= 0xf03f;
|
|
temp |= 2 << 9; /* 36 ohm */
|
|
temp |= 2 << 6; /* 39 ohm */
|
|
|
|
err = phy_write(phydev, 0x1e, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, 0x1d, 0x3);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, 0x1e, 0x8000);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
}
|
|
|
|
err = marvell_of_reg_init(phydev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* marvell_read_status
|
|
*
|
|
* Generic status code does not detect Fiber correctly!
|
|
* Description:
|
|
* Check the link, then figure out the current state
|
|
* by comparing what we advertise with what the link partner
|
|
* advertises. Start by checking the gigabit possibilities,
|
|
* then move on to 10/100.
|
|
*/
|
|
static int marvell_read_status(struct phy_device *phydev)
|
|
{
|
|
int adv;
|
|
int err;
|
|
int lpa;
|
|
int status = 0;
|
|
|
|
/* Update the link, but return if there
|
|
* was an error */
|
|
err = genphy_update_link(phydev);
|
|
if (err)
|
|
return err;
|
|
|
|
if (AUTONEG_ENABLE == phydev->autoneg) {
|
|
status = phy_read(phydev, MII_M1011_PHY_STATUS);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
lpa = phy_read(phydev, MII_LPA);
|
|
if (lpa < 0)
|
|
return lpa;
|
|
|
|
adv = phy_read(phydev, MII_ADVERTISE);
|
|
if (adv < 0)
|
|
return adv;
|
|
|
|
lpa &= adv;
|
|
|
|
if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
|
|
phydev->duplex = DUPLEX_FULL;
|
|
else
|
|
phydev->duplex = DUPLEX_HALF;
|
|
|
|
status = status & MII_M1011_PHY_STATUS_SPD_MASK;
|
|
phydev->pause = phydev->asym_pause = 0;
|
|
|
|
switch (status) {
|
|
case MII_M1011_PHY_STATUS_1000:
|
|
phydev->speed = SPEED_1000;
|
|
break;
|
|
|
|
case MII_M1011_PHY_STATUS_100:
|
|
phydev->speed = SPEED_100;
|
|
break;
|
|
|
|
default:
|
|
phydev->speed = SPEED_10;
|
|
break;
|
|
}
|
|
|
|
if (phydev->duplex == DUPLEX_FULL) {
|
|
phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
|
|
phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
|
|
}
|
|
} else {
|
|
int bmcr = phy_read(phydev, MII_BMCR);
|
|
|
|
if (bmcr < 0)
|
|
return bmcr;
|
|
|
|
if (bmcr & BMCR_FULLDPLX)
|
|
phydev->duplex = DUPLEX_FULL;
|
|
else
|
|
phydev->duplex = DUPLEX_HALF;
|
|
|
|
if (bmcr & BMCR_SPEED1000)
|
|
phydev->speed = SPEED_1000;
|
|
else if (bmcr & BMCR_SPEED100)
|
|
phydev->speed = SPEED_100;
|
|
else
|
|
phydev->speed = SPEED_10;
|
|
|
|
phydev->pause = phydev->asym_pause = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m88e1121_did_interrupt(struct phy_device *phydev)
|
|
{
|
|
int imask;
|
|
|
|
imask = phy_read(phydev, MII_M1011_IEVENT);
|
|
|
|
if (imask & MII_M1011_IMASK_INIT)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
|
|
{
|
|
wol->supported = WAKE_MAGIC;
|
|
wol->wolopts = 0;
|
|
|
|
if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
|
|
MII_88E1318S_PHY_WOL_PAGE) < 0)
|
|
return;
|
|
|
|
if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
|
|
MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
|
|
wol->wolopts |= WAKE_MAGIC;
|
|
|
|
if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
|
|
return;
|
|
}
|
|
|
|
static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
|
|
{
|
|
int err, oldpage, temp;
|
|
|
|
oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
|
|
|
|
if (wol->wolopts & WAKE_MAGIC) {
|
|
/* Explicitly switch to page 0x00, just to be sure */
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Enable the WOL interrupt */
|
|
temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
|
|
temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
|
|
MII_88E1318S_PHY_LED_PAGE);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Setup LED[2] as interrupt pin (active low) */
|
|
temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
|
|
temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
|
|
temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
|
|
temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
|
|
MII_88E1318S_PHY_WOL_PAGE);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Store the device address for the magic packet */
|
|
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
|
|
((phydev->attached_dev->dev_addr[5] << 8) |
|
|
phydev->attached_dev->dev_addr[4]));
|
|
if (err < 0)
|
|
return err;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
|
|
((phydev->attached_dev->dev_addr[3] << 8) |
|
|
phydev->attached_dev->dev_addr[2]));
|
|
if (err < 0)
|
|
return err;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
|
|
((phydev->attached_dev->dev_addr[1] << 8) |
|
|
phydev->attached_dev->dev_addr[0]));
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Clear WOL status and enable magic packet matching */
|
|
temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
|
|
temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
|
|
temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
|
|
if (err < 0)
|
|
return err;
|
|
} else {
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
|
|
MII_88E1318S_PHY_WOL_PAGE);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* Clear WOL status and disable magic packet matching */
|
|
temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
|
|
temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
|
|
temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
|
|
err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver marvell_drivers[] = {
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1101,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1101",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1112,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1112",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1111_config_init,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1111,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1111",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1111_config_init,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &marvell_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1118,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1118",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1118_config_init,
|
|
.config_aneg = &m88e1118_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = {.owner = THIS_MODULE,},
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1121R,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1121R",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_aneg = &m88e1121_config_aneg,
|
|
.read_status = &marvell_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.did_interrupt = &m88e1121_did_interrupt,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1318S,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1318S",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_aneg = &m88e1318_config_aneg,
|
|
.read_status = &marvell_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.did_interrupt = &m88e1121_did_interrupt,
|
|
.get_wol = &m88e1318_get_wol,
|
|
.set_wol = &m88e1318_set_wol,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1145,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1145",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1145_config_init,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1149R,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1149R",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1149_config_init,
|
|
.config_aneg = &m88e1118_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1240,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1240",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1111_config_init,
|
|
.config_aneg = &marvell_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1116R,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1116R",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_init = &m88e1116r_config_init,
|
|
.config_aneg = &genphy_config_aneg,
|
|
.read_status = &genphy_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
{
|
|
.phy_id = MARVELL_PHY_ID_88E1510,
|
|
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
|
.name = "Marvell 88E1510",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
.config_aneg = &m88e1510_config_aneg,
|
|
.read_status = &marvell_read_status,
|
|
.ack_interrupt = &marvell_ack_interrupt,
|
|
.config_intr = &marvell_config_intr,
|
|
.did_interrupt = &m88e1121_did_interrupt,
|
|
.driver = { .owner = THIS_MODULE },
|
|
},
|
|
};
|
|
|
|
static int __init marvell_init(void)
|
|
{
|
|
return phy_drivers_register(marvell_drivers,
|
|
ARRAY_SIZE(marvell_drivers));
|
|
}
|
|
|
|
static void __exit marvell_exit(void)
|
|
{
|
|
phy_drivers_unregister(marvell_drivers,
|
|
ARRAY_SIZE(marvell_drivers));
|
|
}
|
|
|
|
module_init(marvell_init);
|
|
module_exit(marvell_exit);
|
|
|
|
static struct mdio_device_id __maybe_unused marvell_tbl[] = {
|
|
{ MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, marvell_tbl);
|